Verilog Jobs

VLSI Systems Faculty Immediate Hiring Job Opportunity:Walk-In Interview for VLSI Engineer (Trainer)Date: 13th September 2025Time: 11:00 AM 2:00 PmBE/B.Tech/ME/M.Tech/BSc/MSc in ECE, EEE, or EIECandidates from Anna University, Tamil Nadu preferredFreshers and experienced candidates welcomeMinimum 70% in graduation and at least 65% in 10th and 12thJob Role:Train fresh engineering graduates in VLSITeach VLSI programming and practical projectsWork on R&D, prototypes, and industry projectsLearn new tech like AI/ML and advanced Embedded SystemsGuide students for their career in VLSISkills Needed:Positive attitude and good academicsGood communicationWillingness to learn new technologiesInterest in FPGA, ASIC, SoC, Verilog, RTL, SystemVerilog, UVMSalary (3-year contract):18,000/month starting4,000 increase after each yearAbout MIET:MIET is a training institute specializing in embedded systems, helping freshers start careers since 2011.Interview Location:Mirror Institute For Embedded Technology184/2, 3rd Floor, Chandamama Building,Arcot Rd, Vadapalani, Chennai 600026(Opposite Kamala Theater, Upstairs to Viveks Showroom)Website: www.lastbenchindia.comContact: 93809 48474Only eligible and interested candidates should attend.

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Requirements often include:Strong proficiency in Verilog/VHDL or SystemVerilog.Knowledge of digital design principles.Understanding of ASIC design flows.Experience with synthesis, place and route tools.Knowledge of FPGA architectures.Experience with FPGA design tools.Understanding of timing analysis and optimization.Knowledge of verification methodologies (e.g., UVM).Experience with simulation tools.Ability to write test benches and develop test plansTools:Synthesis Tools:Synopsys Design Compiler: A widely used synthesis tool.Cadence Genus Synthesis Solution: Another industry-standard tool.Xilinx Vivado: Includes synthesis tools for Xilinx FPGAs.Intel Quartus Prime: Includes synthesis tools for Intel FPGAs.Simulators:Verilator:Icarus Verilog: A free and open-source Verilog simulation and synthesis tool.For any further query kindly contact: Hemath Kumar :-8496929937.Job Types: Full-time, InternshipContract length: 21 monthsPay: 160,000.00 - 430,000.00 per yearBenefits:Health insuranceProvident FundSchedule:Day shiftSupplemental Pay:Performance bonusWork Location: In personApplication Deadline: 15/03/2025

A broad career platform- Cross regional and multi business development opportunities, equal achievement for everyone. A free working atmosphere- Flexible working hours and equal communication mechanism. Superior work benefits- Rich rewards and competitive remunerationIf this is a journey youd like to embark on, keep reading!In this position you will:The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.Requirements:-Bachelor Degree or M.S. in Electrical Engineering or Microelectronics.-5y & above exp with pre-silicon UVM experienceThe candidate should have good understanding on ASIC/SOC design flow and should have: 1. Strong coding with Verilog and SystemVerilog2. Good knowledge of design verification methodology UVM.3. Many experiences with sequence creation, functional cover groups and assertion coding.4. Strong C/C++ software development experiences5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby.

Hiring for 31 Information Technology Architect Jobs in Shimla,Patna,Bengaluru,Kohima,Chennai,Bhuleshwar, Mumbai,Jaipur,Padri Bazar, Gorakhpur,Visakhapatnam,Baloda Bazar, for Freshers,Required Educational Qualification is : B.A, B.C.A, B.Com, B.Ed, B.Sc, B.E, B.Tech, MBBS, Post Graduate Diploma, M.Sc with Good knowledge in Problem Solving,Communication,Web Analyzer,System Verilog,E-commerce,Marketing,Branch Sales,Time Management etc.

1. 4 to 6 Years of Experience.2. Strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology3. Experience on development of Testbench from scratch and knowledge of DUT integration with verification environment.4. Good knowledge of various EDA tools (Cadence/Synopsys/Mentor)5. Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI 6. Good knowledge of scripting languages like shell/perl/python/Makefile etc.

Designation: Member Technical StaffNo.of positions: 7Experience : 3-13 YearsEducation: MTech VLSI / BE. ECEIndustry Type: Education / E-Learning / SemiconductorFunctional Area: Trainingcategory: TechnicalFilter: Full-timeJob DescriptionExtensive hands-on and teaching experience in Digital / SV /UVM/ Verilog / VHDL /DFT toolsExtensive experience in Back-end designExperience in Mentor Graphics EDA flow is an added advantageResponsible for the development and support of Projects.Responsible for Debugging the source codes in Verilog, SV, and UVM.Responsible for Training Delivery and SupportDesired Candidate ProfileSound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design3 to 8 years industry/teaching experienceGood communication skillSalary:- 5 - 8LPA

Hello VLSI Professionals!!!We are hiring below positions:*Physical Design Engineer*Physical Verification Engineer*RTL Design Engineer*Design & verification Engineer*FPGA Design Engineer*DFT Engineer*Emulation Engineer*STA & SynthesisExperience Level : 3+ Years in relevance. (Freshers can also apply for Intern)Notice Period : Immediate-60 days.Work Location : Bangalore, Hyderabad and Chennai**Selected candidates will receive call letter for Technical rounds**VLSI design has a promising future with several exciting trends and technologies emerging in the field. One of the key trends is the integration of System-on-Chip (SoC), which involves combining multiple functionalities onto a single chip. This integration enables higher performance, increased power efficiency, and reduced form factors for electronic devices.Another noteworthy trend is the continuous scaling down of transistor dimensions, which has been the driving force behind the historical growth of IC computing power. Shrinking transistor dimensions allows for increased transistor density and improved device performance. However, as transistor sizes approach their physical limits, alternative design and manufacturing techniques such as nanoscale technologies and 3D integration are being explored to further enhance the capabilities of VLSI systems.Additionally, VLSI design is closely tied with related fields such as artificial intelligence (AI) and Internet of Things (IoT). The growing demand for AI and IoT applications is pushing the development of VLSI systems that can support the processing and connectivity requirements of these technologies.

1.HDL-verilog,VHDL,TOOLS-intel quartus-2,xilinx vivado and xilinx vitis IDE,DEBUGGERS-xilinx J-tag tools,intel quartus-2 debugger,TESTBENCH SKILLS-system verilog and other methodologies ,RTL design as per RTL life cycle,design,development ,test etc ,problem solving with hardware designs,troubleshoot /debug hardwaredesign/board problems.

Job DescriptionExtensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT toolsExtensive experience in Back-end designExperience on Mentor Graphics EDA flow is an added advantageResponsible for development and support of Projects.Responsible for Debugging the source codes in Verilog, SV, and UVM.Responsible for Training Delivery and SupportDesired Candidate ProfileSound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design3 to 8 years industry/teaching experienceGood communication skill

1. Brining up Linux environment on ARM2. Work will involve interfacing with a camera, display, and some image processing.3. Design implementation (FPGA design and simulation)4. Rapid prototyping, bring up and debug5. Comfortable in Linux environment.Note: Self-motivated, goal oriented and good analytical skills

RTL(Verilog) and SV/UVM Concept and Practical knowledge / Regression using Venus & Granite setup/ Coverage/ UPF/Latency/PerformanceProtocol Knowledge DDR5/EMMC/USB/GBE/AXI4/APB/AHB/DFTKnowledge on Venus & Granite setup and Coverage/ UPF/Latency/PerformanceEmulation expertise in zebu platform and SimicsExperience in C/C++ and scripting tcl/perlBackground in FPGA/SOC design and Verification

Work Location: Bangalore / Hyderabad / Coimbatore. EXP- 5+Design Verification - Strong UVM/SV- IP and SOC DV- AXI- 5+ need to have strong protocol Exp such as DDR. PCIe, EthernetDesign Verification - Gate Level Simulations (GLS)- Gate Level Simulation (GLS) knowledge is must- IP and SOC DV- 5+ need to have strong GLS expRTL Design - NO FPGA engineers. They shall have worked on ASIC flow- Keywords - SPYGLASS, LEC, LINT, Synthesis,Emulation - UVM/SV- Synopsys Zebu- Transactor development OR running design with Firmware on ZebuFORMAL - Design Verification - Strong UVM/SV- Experience on Cadence Jasper Gold or Incisive formal verifier (IFV)- Connectivity Check, Register Validation etc.- 7+ need to have some protocol

IP verification Using SV/UVM SOC Verification using C/SV Third Party VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (3+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+) Memory Interfaces: DDR or HBM I/O (10+) Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incsive Technical Documentation: Testbench Specification, Test Plan Specification Foundry Porting Experience: Technology Library Conversion Related Changes Verification

About Company :SiMa is a machine learning company transforming the embedded edge market through high-performance compute at the lowest power. Initially focused on computer vision applications, the company's software-first approach simplifies ML integration and supports the broadest set of capabilities through a purpose-built MLSoC platform, enabling rapid adoption and creating the best of ease-of-use experience. SiMa.ai is led by technologists and business veterans and backed by a set of top investors committed to helping customers scale machine learning at the edge. For more informationJob Description :- As the Hardware Design Verification Engineer, you will help lead and develop the verification methodology for SiMa.ai's MLSoC- .- As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support.- You will work very closely with the Architecture, RTL/uArch, and cross-functional teams.Areas of focus :Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team.Minimum Qualifications :- BS in Computer Science/EE with 15+ years of experience or MS in Computer Science/EE with 12+ years of experience in HW Design Verification.- Experience with block level, cluster level or chip/SoC level verification.- Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, System Verilog.- Expertise in scripting languages, python or perl.- Strong experience in helping emulation and validation.- Experience with modeling various HW blocks, IPs for verification, emulation.- Ability to analyze systems-level performance, profiling, and analysis.

Open Positions: RTL DESIGN EngineerEducation: M.Tech (2022, 2021,2020,2019,2018 .........)B.Tech (2020, 2019,2018,2017...........)Skills Required: Strong in Digital Electronics & Verilog.Knowledge in LINT, CDC, Spyglass would be an added advantage.Experience: 0-4 YearsLocation: Hyderabad / BangaloreAvailability: Immediate

Key Qualification 4+ years of experience with large FPGA development on Xilinx / Altera/ Microsemi Devices 4+ years of RTL development using Verilog / VHDL/ System-Verilog/UVM /C/C++ Well versed with FPGA design flow including design entry, synthesis, Implementation, place and route, timing constraints and timing closure In-depth background in HDL development, Verilog coding, integration, synthesis, debug, simulation, test bench creation Experienced with test planning, test bench architecture and assertions Constrained random verification experience with SystemVerilog and UVM Coverage driven verification (code/functional/assertion coverage) Demonstrated experience working on FPGA design projects, including work with SoC (ARM/RISC-V CPU), 10/ 40/ 100G Ethernet PHY, DDR#, PCI-E, SDIO interfaces. Hands on experience with lab debug equipment, such as oscilloscopes, logic analyzers, soldering Effectively communicate with cross functional team for bringing up designs Good knowledge with high speed bus protocols including AMBA/AXI3/AXI4 and low speed protocols including USB / SPI / UART/ IIC and other native protocols Experienced with ADC / DAC / EEPROM and other peripheral componentsPreferred Experience with SERDES / JESD204B /Gb PHY is PLUS Ability to communicate and work well with team Excellent interpersonal skills and self-motivation Ability to work well in a team and be productive under tight schedules Knowledge of computer architecture is plus Excellent written and verbal communication skills PCB-Schematic Reading Full Design Integration and debug Good understanding of low-level software and device drivers such as Firmware, Boot.

Experience in Digital Signal Processing (DSP). Experience in FPGA and VHDL /Verilog Programming, Experience in Xilinx tool chain and FPGA based hardware testingYou Can Contact me if you have any quires.Regards,Sathya -HR

Required VLSI dsign engineers in DV, PD, DFT, Analog layout. Interested candidates send your resume

This role is an exciting opportunity for a ASIC designer to contribute in a team of highly skilled design engineers within the SouthBridge IO (SBIO) team. Provide IP technical management and support for the end-to-end design development flow. This includes from architecture, microarchitecture, RTL design, design metrics (performance, power, area) analysis and design for verification strategy. Collaborate with design and verification teams to ensure a predictable IP development. Exhibits relentless commitment to help the team meet quality and development goals on schedule Drives to learn and perform at his or her highest potential in a technical capacity Thrives in both a team environment and in individual contribution Communicates openly and clearly in meetings, presentations, emails, and reports Able to learn independently and acquire new skills required for the job Creative and innovator and thinker who loves technical problems and detail-oriented tasksKEY RESPONSIBLITIES: IP RTL design for USB IP used for all next generation server, clients, GPU and Semicustom products. Work closely with IP and system architects to micro-architect cutting edge features. Apply low power design techniques to existing logic and maintain overall systemperformance. Focus on timing, LINT and CDC closure to ensure high quality RTL. Support verification and debug of the ASIC throughout various stages of the project. Jump into the lab and solve post silicon bring-up or customer issues. Analyzecomplex digital design problems and propose solutions. Develop Verilog RTL and Functional Behavioral Models. Drive/develop ASIC design flows and scripts. Create microarchitecture specifications. Work with Design Verification team to ensure functional correctness. Work with Physical Design team to ensure proper implementation of the design along with timing closure. Deliver improvements, optimization and power saving enhancements. At least 4 years experience