VLSI Design Engineer

AdvanSoft

5 - 9 Years
100 Openings
15.0 - 40.0 Lac/Yr
Face-to-Face interview
Hyderabad

Key Skills

C Language VLSI-Very Large Scale Integration EDA System Verilog ASIC Verification RTL GLS UVM

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Job Description

work location: bangalore / hyderabad / coimbatore.

exp- 5+

design verification

- strong uvm/sv

- ip and soc dv

- axi

- 5+ need to have strong protocol exp such as ddr. pcie, ethernet

design verification - gate level simulations (gls)

- gate level simulation (gls) knowledge is must

- ip and soc dv

- 5+ need to have strong gls exp

rtl design

- no fpga engineers. they shall have worked on asic flow

- keywords - spyglass, lec, lint, synthesis,

emulation

- uvm/sv

- synopsys zebu

- transactor development or running design with firmware on zebu

formal - design verification

- strong uvm/sv

- experience on cadence jasper gold or incisive formal verifier (ifv)

- connectivity check, register validation etc.

- 7+ need to have some protocol