key qualification
• 4+ years of experience with large fpga development on xilinx / altera/ microsemi devices
• 4+ years of rtl development using verilog / vhdl/ system-verilog/uvm /c/c++
• well versed with fpga design flow including design entry, synthesis, implementation, place and
route, timing constraints and timing closure
• in-depth background in hdl development, verilog coding, integration, synthesis, debug, simulation,
test bench creation
• experienced with test planning, test bench architecture and assertions
• constrained random verification experience with systemverilog and uvm
• coverage driven verification (code/functional/assertion coverage)
• demonstrated experience working on fpga design projects, including work with soc (arm/risc-v
cpu), 10/ 40/ 100g ethernet phy, ddr#, pci-e, sdio interfaces.
• hands on experience with lab debug equipment, such as oscilloscopes, logic analyzers, soldering
• effectively communicate with cross functional team for bringing up designs
• good knowledge with high speed bus protocols including amba/axi3/axi4 and low speed protocols
including usb / spi / uart/ iic and other native protocols
• experienced with adc / dac / eeprom and other peripheral components
preferred
• experience with serdes / jesd204b /gb phy is plus
• ability to communicate and work well with team
• excellent interpersonal skills and self-motivation
• ability to work well in a team and be productive under tight schedules
• knowledge of computer architecture is plus
• excellent written and verbal communication skills
• pcb-schematic reading
• full design integration and debug
• good understanding of low-level software and device drivers such as firmware, boot.