FPGA Design Engineer

Idexcel
  • icon job experience 3 - 8 Years
  • icon job opening 5 Openings
  • icon salary Not Disclosed
  • Face-to-Face interview Face-to-Face interview
  • icon job location Bangalore
Key Skills

Verilog RTL Coding FPGA Design

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Job Description

RTL(Verilog) and SV/UVM Concept and Practical knowledge / Regression using Venus & Granite setup/ Coverage/ UPF/Latency/Performance

Protocol Knowledge – DDR5/EMMC/USB/GBE/AXI4/APB/AHB/DFT

Knowledge on Venus & Granite setup and Coverage/ UPF/Latency/Performance

Emulation expertise in zebu platform and Simics

Experience in C/C++ and scripting tcl/perl

Background in FPGA/SOC design and Verification

  • Experience

    3 - 8 Years

  • No. of Openings

    5

  • Education

    Graduate

  • Role

    FPGA Design Engineer

  • Industry Type

    IT-Hardware & Networking

  • Gender

    [ Male / Female ]

  • Job Country

    India

  • Type of Job

    Full Time

  • Work Location Type

    Work from Office

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About Idexcel

Idexcel is a Professional Services and Technology Solutions provider specializing in Cloud Services, Cloud Native Services, Data Platforms and Intelligence, Automation & AI. Idexcel is an Amazon Web Services (AWS) Advanced Tier Services Partner. We as Idexcel, are proud that for more than 20 years we have provided services that implement complex technologies that are innovative, agile and successful and have provided our customers with lasting value.
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