Design & Verification Engineer

Thundersoft

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in this position you will:

the successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product time to market for asic/soc design. he/she should be able to work independently on various dv tasks and providing technical guidance to the dv team. the candidate would involve technically in the porting/creation of the dv environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.

requirements:

-bachelor degree or . in electrical engineering or microelectronics.

-5y & above exp with pre-silicon uvm experience

the candidate should have good understanding on asic/soc design flow and should have:

1. strong coding with verilog and systemverilog

2. good knowledge of design verification methodology uvm.

3. many experiences with sequence creation, functional cover groups and assertion coding.

4. strong c/c++ software development experiences

5. be familiar with scripting language, such as perl, c shell, makefile, ruby.

• Experience

  4 - 8 Years

• No. of Openings

  1

• Education

  Professional Degree

• Role

  Design & Verification Engineer

• Industry Type

  Manufacturing / Production / Quality

• Gender

  [ Male / Female ]

• Type of Job

  Full Time

• Work Location Type

  Work from Office