Design & Verification Engineer

Key Skills

Uvm Systemverilog Verification Engineer Pcie Ethernet Ddr Vhdl System Verilog Cxl Amba Python

Job Description

1. 4 to 6 years of experience.

2. strong sv and uvm knowledge. hands-on experience on soc/sub-system /block level verification, knowledge of coverage-driven methodology

3. experience on development of testbench from scratch and knowledge of dut integration with verification environment.

4. good knowledge of various eda tools (cadence/synopsys/mentor)

5. experience on protocols like pcie/usb/ucie/cxl/ethernet/amba/mipi

6. good knowledge of scripting languages like shell/perl/python/makefile etc.
  • Experience

    5 - 10 Years

  • No. of Openings

    1

  • Education

    Higher Secondary, Any Bachelor Degree

  • Role

    Design & Verification Engineer

  • Industry Type

    Manufacturing / Production / Quality

  • Gender

    [ Male / Female ]

  • Job Country

    India

  • Type of Job

    Full Time

  • Work Location Type

    Work from Office

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