FPGA Design and Verification Validation Engineer ( 2 - 6 yrs)
Posted on 36 days ago
RS Not disclosed Hyderabad, Bangalore
Location :- Bengaluru / Hyderabad No. Of Positions - 2 Experience:- RTL Design 2+ Years IP Verification 2+ Years IP Design/ SOC Design 4+ Years FPGA Design 6+ Years Job Description: Independent In-charge of the FPGA D...
Key Skills : RTL Coding,IP veification,IP Design,Soc design,FPGA Design,mipi,ODR,DDR2
ASIC Design Verification Engineer ( 3 - 5 yrs)
Posted on 90 days ago
Global Talent Pool
RS 6,00,000 To 15,00,000 p.a. Bangalore
knowledge with prior work experience on live projects. Expertise in creating detailed test plan with well-defined functional coverage. • Should be able to architect and implement self generating / self checking simulation verificati...
Key Skills : uvm,sv,design verification engineer,design engineer
Design Engineer ASIC SOC Verification ( 4 - 10 yrs)
RS 1,50,000 To 4,25,000 p.a. Bangalore, Kochi, Pune, Noida
• You will be part of the team verifying IPs and SoCs leading to first Si success. • IP verification is coverage driven using latest industry standard methodologies and HVLs. • Work involves defining verification strategy, writing test pl...
Key Skills : Design Engineer,C,C++
Design Verification Engineer ( 3 - 9 yrs)
RS 50,000 To 15,00,000 p.a. Hyderabad, Bangalore
Design Verification • Very good system Verilog /UVM/OVM knowledge with prior work experience on live projects • Good logical thinking and excellent at solving the digital logic • Must have hands on experience in complete IP/SoC Verific...
Key Skills : uvm,syetemverilog,asic designing,design,design verification
RTL Design and verification Engineer ( 3 - 7 yrs)
RS 5,00,000 To 13,00,000 p.a. Bangalore
• Develop micro-architecture and RTL implementation. • Block level/ full chip integration and design. • Hands-on with Lint, CDC , LEC and preferably Low Power check tools • Some experience of AXI/AHB • design in System Verilog and timin...
Key Skills : ASIC Synthesis,ASIC Design,lint,cdc,Synthesis,Verilog,ovm,uvm,RTL,Verification Engineer,RTL design
Design Verification Engineers ( 3 yrs)
Synapse Techno Design Innovations
RS 1,00,000 To 3,00,000 p.a. Bangalore
DV Engineers having experience in (System Verilog, UVM) Experience 3 Years to 8 Years Job Locations Bangalore, Shanghai, JD:- a ) SoC based verification: - Must have working knowledge of Verilog , System Verilog (HVL)
Key Skills : system verilog,uvm,ovm,axi,ace,ahb,apb,verilog,amba,...
Design Verification Engineer ( 8 yrs)
Eliteplus Semiconductor Technologies Pvt Ltd
RS 10,00,000 To 20,00,000 p.a. Bangalore
- Minimum 4 years of experience in Design Verification - Working experience in IP / SoC verification - Should have the expertise to develop block level / system level verification environments using System Verilog and UVM / OVM - Experience to de...
Key Skills : Design Associate
Required Design Verification Engineer Internship ( 1 yrs)
Will be responsible to design the RTL codes and verify them using System Verilog and UVM.
Key Skills : Verification Engineer,Design Engineering,Verilog