responsibilities:
lead end-to-end verification from complex cpu sub-units up to cpu clusters, partnering with architecture and design teams
develop verification infrastructure components including test-benches, scoreboards, and stimulus generators
develop and execute comprehensive verification plans for units and features
implement functional coverage models
debug designs in simulation, prototyping platforms, and silicon
continuously drive methodology improvements to improve efficiency
lead senior and junior engineers as a team to accomplish successful projects
minimum qualifications:
bachelors or masters degree in electrical, computer engineering or related field
bs+10 years or ms+12 years of industry experience successfully delivering cpu implementations
skills & qualifications required:
system verilog verification development experience
test bench construction using uvm or analogous methodologies
scoreboards and stimulus generators for complex units
strong background in one or more common cpu isas. x86, arm, mips, risc-v, etc.
strong background in processor coherency and mp programming
project ownership throughout the project lifecycle demonstrated team leadership experience with outstanding communication skills highly motivated self-starter with strong execution mindset and collaborative approach
post-silicon debug experience strongly preferred