Design & Verification Engineer Jobs

Responsibilities:Lead end-to-end verification from complex CPU sub-units up to CPU clusters, partnering with architecture and design teamsDevelop verification infrastructure components including test-benches, scoreboards, and stimulus generatorsDevelop and execute comprehensive verification plans for units and featuresImplement functional coverage modelsDebug designs in simulation, prototyping platforms, and siliconContinuously drive methodology improvements to improve efficiencyLead senior and junior engineers as a team to accomplish successful projectsMinimum Qualifications: Bachelors or Masters degree in electrical, computer engineering or related fieldBS+10 years or MS+12 years of industry experience successfully delivering CPU implementationsSkills & Qualifications Required: System Verilog verification development experienceTest bench construction using UVM or analogous methodologiesScoreboards and stimulus generators for complex unitsStrong background in one or more common CPU ISAs. x86, ARM, MIPS, RISC-V, etc.Strong background in processor coherency and MP programmingProject ownership throughout the project lifecycle Demonstrated team leadership experience with outstanding communication skills Highly motivated self-starter with strong execution mindset and collaborative approachPost-silicon debug experience strongly preferred

A broad career platform- Cross regional and multi business development opportunities, equal achievement for everyone. A free working atmosphere- Flexible working hours and equal communication mechanism. Superior work benefits- Rich rewards and competitive remunerationIf this is a journey youd like to embark on, keep reading!In this position you will:The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.Requirements:-Bachelor Degree or M.S. in Electrical Engineering or Microelectronics.-5y & above exp with pre-silicon UVM experienceThe candidate should have good understanding on ASIC/SOC design flow and should have: 1. Strong coding with Verilog and SystemVerilog2. Good knowledge of design verification methodology UVM.3. Many experiences with sequence creation, functional cover groups and assertion coding.4. Strong C/C++ software development experiences5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby.

Working Requirements -:- Approval of Drawings -:- Study design input , any ambiguity discuss with Team leaderPrepare General arrangement drawings and SLD and get it reviewed.Verify Bill of material Report and export to SAPGet drawing checked from Team Leader DesignUpdate status in Master drg. List in SAPSent Drawing for Approval -:- Prepare PDF copy of drawings sent to team Leader for futher processIf hard copy required prepare transmittal and drawing folder and sent for approvalCopy Rev. '0' drawings and revise the drawings as per comments received.Revision in Drawings -:- Any issue in the comments , discuss with Team leadersend drawing for re-approval through team leaderProcurement Release -:- Release BOM to PPC/Purchase after the material clearance received from clientDrawing release for manufacturer -:- when approved drawings are received , prepare PDF in release drawing folder and release the SAP BOQProvide and release the drawings to PPC/Production/FabricationAddition/ Deletion -:- Prepare Addition deletion statement within 1 days of drawing release .Get it checked and verified from Team leaderScheme Drawing preparation -:- Prepare scheme drawing and get it checked from Team leaderMaintain all revised drawing in Master drawing folderMaintenance of Drawing records -:- Keep stamped / approved drawings in master drg. folder. Wherever hard copy is received, keep scan copy for record.Update job status in master drawing list in SAPMaintain IMS records of job handledMIS -:- Update all records in MIS at the end of month.

1. 4 to 6 Years of Experience.2. Strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology3. Experience on development of Testbench from scratch and knowledge of DUT integration with verification environment.4. Good knowledge of various EDA tools (Cadence/Synopsys/Mentor)5. Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI 6. Good knowledge of scripting languages like shell/perl/python/Makefile etc.

Job DescriptionResponsibilities:Preparation of digital design test plan from requirements using Cadence-vManager / vPlannerDefinition and creation of UVM-SV test environment, test plans, tests, and functional coverageVerification of signal processing and control algorithms using Cadence and MathWorks toolsAnalysis of test results, improving test coverage, and debug of unexpected design behaviorRunning and maintenance of regression runs0p-Preparation and/or leading of verification reviewsModification and/or debug of Simulink models in mixed signal test environmentCoordination of verification activities with abroad team membersCooperation with system engineering team on Jama requirementsMandatory skills:Possess at least a BSEE (MSEE preferred)Should have 6-8yrsl years' experience in digital design and/or digital verificationMust be knowledgeable in digital design fundamentalsKnowledge of Universal Verification Methodology, System Verilog assertions, and Cadence verification tools is a mustExperience with the usage of Jama requirements management, MATLAB/Simulink model, and Python programming is a strong plus

Job DescriptionResponsibilities:Preparation of digital design test plan from requirements using Cadence-vManager / vPlannerDefinition and creation of UVM-SV test environment, test plans, tests, and functional coverageVerification of signal processing and control algorithms using Cadence and MathWorks toolsAnalysis of test results, improving test coverage, and debug of unexpected design behaviorRunning and maintenance of regression runs0p-Preparation and/or leading of verification reviewsModification and/or debug of Simulink models in mixed signal test environmentCoordination of verification activities with abroad team membersCooperation with system engineering team on Jama requirementsMandatory skills:Possess at least a BSEE (MSEE preferred)Should have 6-8yrsl years' experience in digital design and/or digital verificationMust be knowledgeable in digital design fundamentalsKnowledge of Universal Verification Methodology, System Verilog assertions, and Cadence verification tools is a mustExperience with the usage of Jama requirements management, MATLAB/Simulink model, and Python programming is a strong plusSkills, Knowledge, and AptitudesExcellent communication, documentation, problem-solving and analytical skills are requiredAble to solve challenging problems during verification and debugAbility to supervise and mentor junior engineers

Hello VLSI Professionals!!!We are hiring below positions:*Physical Design Engineer*Physical Verification Engineer*RTL Design Engineer*Design & verification Engineer*FPGA Design Engineer*DFT Engineer*Emulation Engineer*STA & SynthesisExperience Level : 3+ Years in relevance. (Freshers can also apply for Intern)Notice Period : Immediate-60 days.Work Location : Bangalore, Hyderabad and Chennai**Selected candidates will receive call letter for Technical rounds**VLSI design has a promising future with several exciting trends and technologies emerging in the field. One of the key trends is the integration of System-on-Chip (SoC), which involves combining multiple functionalities onto a single chip. This integration enables higher performance, increased power efficiency, and reduced form factors for electronic devices.Another noteworthy trend is the continuous scaling down of transistor dimensions, which has been the driving force behind the historical growth of IC computing power. Shrinking transistor dimensions allows for increased transistor density and improved device performance. However, as transistor sizes approach their physical limits, alternative design and manufacturing techniques such as nanoscale technologies and 3D integration are being explored to further enhance the capabilities of VLSI systems.Additionally, VLSI design is closely tied with related fields such as artificial intelligence (AI) and Internet of Things (IoT). The growing demand for AI and IoT applications is pushing the development of VLSI systems that can support the processing and connectivity requirements of these technologies.

About Company :SiMa is a machine learning company transforming the embedded edge market through high-performance compute at the lowest power. Initially focused on computer vision applications, the company's software-first approach simplifies ML integration and supports the broadest set of capabilities through a purpose-built MLSoC platform, enabling rapid adoption and creating the best of ease-of-use experience. SiMa.ai is led by technologists and business veterans and backed by a set of top investors committed to helping customers scale machine learning at the edge. For more informationJob Description :- As the Hardware Design Verification Engineer, you will help lead and develop the verification methodology for SiMa.ai's MLSoC- .- As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support.- You will work very closely with the Architecture, RTL/uArch, and cross-functional teams.Areas of focus :Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team.Minimum Qualifications :- BS in Computer Science/EE with 15+ years of experience or MS in Computer Science/EE with 12+ years of experience in HW Design Verification.- Experience with block level, cluster level or chip/SoC level verification.- Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, System Verilog.- Expertise in scripting languages, python or perl.- Strong experience in helping emulation and validation.- Experience with modeling various HW blocks, IPs for verification, emulation.- Ability to analyze systems-level performance, profiling, and analysis.

1. Brining up Linux environment on ARM2. Work will involve interfacing with a camera, display, and some image processing.3. Design implementation (FPGA design and simulation)4. Rapid prototyping, bring up and debug5. Comfortable in Linux environment.Note: Self-motivated, goal oriented and good analytical skills

Job descriptionThe candidate will have a key role in architecture and development of advanced verification environments for complex SoC components, while ensuring on time, one time best-in-class quality. The candidate will have a significant opportunity to interact with system design teams across geographies.Job Requirements An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans Analog mixed signal experience and analog modeling is a strong plus. Relevant experience with one or more of PCIe, NVMe, NAND, DDR, and CPU sub-systems. Work experience in I2C, USB 3.0, AXI, PCIe, SPI, Ethernet etc. desired Deep understanding and knowledge of verification methodologies, flows and quality metrics. Great debugging and problem-solving skills Work closely with designers to resolve bugs Team player with great interpersonal communication skills. Having an entrepreneur's spirit for growing business an added plusJob Qualifications 5-10+ years relevant experience in SoC verification. 1-2 years experience in leading a small team an added plus Strong and relevant expertise with ASIC simulation tools and advanced verification methods. Expert level in verification languages such as UVM and System Verilog. Relevant experience with writing block-level and SoC test-plans Scripting experience (Python/ Perl/ Tcl) a big plus

IP verification Using SV/UVM SOC Verification using C/SV Third Party VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (3+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+) Memory Interfaces: DDR or HBM I/O (10+) Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incsive Technical Documentation: Testbench Specification, Test Plan Specification Foundry Porting Experience: Technology Library Conversion Related Changes Verification

Work Location: Bangalore / Hyderabad / Coimbatore. EXP- 5+Design Verification - Strong UVM/SV- IP and SOC DV- AXI- 5+ need to have strong protocol Exp such as DDR. PCIe, EthernetDesign Verification - Gate Level Simulations (GLS)- Gate Level Simulation (GLS) knowledge is must- IP and SOC DV- 5+ need to have strong GLS expRTL Design - NO FPGA engineers. They shall have worked on ASIC flow- Keywords - SPYGLASS, LEC, LINT, Synthesis,Emulation - UVM/SV- Synopsys Zebu- Transactor development OR running design with Firmware on ZebuFORMAL - Design Verification - Strong UVM/SV- Experience on Cadence Jasper Gold or Incisive formal verifier (IFV)- Connectivity Check, Register Validation etc.- 7+ need to have some protocol

We have vacant of 90 Design verification Engineer Jobs in Bangalore,Hyderabad,Noida,Chennai Experience Required : 3 Years Educational Qualification : B.Tech/B.E, M.Tech Skill UVM,System Verilog,AXI,AHB,Debug etc.

Key Qualification 4+ years of experience with large FPGA development on Xilinx / Altera/ Microsemi Devices 4+ years of RTL development using Verilog / VHDL/ System-Verilog/UVM /C/C++ Well versed with FPGA design flow including design entry, synthesis, Implementation, place and route, timing constraints and timing closure In-depth background in HDL development, Verilog coding, integration, synthesis, debug, simulation, test bench creation Experienced with test planning, test bench architecture and assertions Constrained random verification experience with SystemVerilog and UVM Coverage driven verification (code/functional/assertion coverage) Demonstrated experience working on FPGA design projects, including work with SoC (ARM/RISC-V CPU), 10/ 40/ 100G Ethernet PHY, DDR#, PCI-E, SDIO interfaces. Hands on experience with lab debug equipment, such as oscilloscopes, logic analyzers, soldering Effectively communicate with cross functional team for bringing up designs Good knowledge with high speed bus protocols including AMBA/AXI3/AXI4 and low speed protocols including USB / SPI / UART/ IIC and other native protocols Experienced with ADC / DAC / EEPROM and other peripheral componentsPreferred Experience with SERDES / JESD204B /Gb PHY is PLUS Ability to communicate and work well with team Excellent interpersonal skills and self-motivation Ability to work well in a team and be productive under tight schedules Knowledge of computer architecture is plus Excellent written and verbal communication skills PCB-Schematic Reading Full Design Integration and debug Good understanding of low-level software and device drivers such as Firmware, Boot.

Experienced in Design Verification minimum 2 Years

Required VLSI dsign engineers in DV, PD, DFT, Analog layout. Interested candidates send your resume

Greetings from Mindtekwe have requirement for Lead and soc verification and Pd engineers for one of the large semiconductor company in bangalore. Interested candidates share your cv.

They have to Design for HVAC & iBMS Independently as per Standards, Knowledge of Standard & Application or Process to be accessed whenever needed, Design Verification from Tools & Software's to be analysed or Developed, Also have to develop Vendors & Benchmark for Tendering & Estimation Process, Management of Vendor with SOP along with Documentation, Identity alternative resources or Options for Projects, Prepare case Studies & Presentation,