RS 10,00,000 To 30,00,000 p.a. Ahmedabad
Minimum 2 years of experience in System Verilog HVL SVA Assertions. Must have executed at-least 2 SoC/IP Formal Verification signoff projects. Must have used Synopsys VC Formal , Cadence Jasper or Questa Formal Tools comprehensively ...
Key Skills : hvl,sva,sv,design verification engineer,design engineer