Design & Verification Engineer Job Vacancies in Surendranagar

1. 4 to 6 Years of Experience.2. Strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology3. Experience on development of Testbench from scratch and knowledge of DUT integration with verification environment.4. Good knowledge of various EDA tools (Cadence/Synopsys/Mentor)5. Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI 6. Good knowledge of scripting languages like shell/perl/python/Makefile etc.

Job descriptionThe candidate will have a key role in architecture and development of advanced verification environments for complex SoC components, while ensuring on time, one time best-in-class quality. The candidate will have a significant opportunity to interact with system design teams across geographies.Job Requirements An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans Analog mixed signal experience and analog modeling is a strong plus. Relevant experience with one or more of PCIe, NVMe, NAND, DDR, and CPU sub-systems. Work experience in I2C, USB 3.0, AXI, PCIe, SPI, Ethernet etc. desired Deep understanding and knowledge of verification methodologies, flows and quality metrics. Great debugging and problem-solving skills Work closely with designers to resolve bugs Team player with great interpersonal communication skills. Having an entrepreneur's spirit for growing business an added plusJob Qualifications 5-10+ years relevant experience in SoC verification. 1-2 years experience in leading a small team an added plus Strong and relevant expertise with ASIC simulation tools and advanced verification methods. Expert level in verification languages such as UVM and System Verilog. Relevant experience with writing block-level and SoC test-plans Scripting experience (Python/ Perl/ Tcl) a big plus