Posted on 10 days agoInfo Corporate Service
RS Not disclosed Bangalore
Dear Folks, we have urgent opening for Software Engineer -C++ programming with OOPS in Bangalore Experience levels of 1 Yrs - 2Yrs C++ • Good in C++ programming with OOPS • Exposure to scripting using perl/python. ...
Key Skills : C++ programming with OOPS,,perl python,System C,hardware modelling and Verilog VHDL
Posted on 13 days agoClavius Solutions
RS Not disclosed China, India
Skills set required: · Expert Knowledge and hands on experience in SOC/IP Verification. · Strong on System Verilog and UVM, C/C++ test cases coding · Should have Excellent debugging skills using VCS ad ...
Key Skills : USB3.0,PCI Express 3.0,802.11 ad,AXI AMBA & SPI protocols,,UVM OVM,System Verilog,OOP,Verilog.
RS 6,00,000 To 18,00,000 p.a. Noida
Looking for a Senior Engineer with 3-7 years of experience in digital design verification domain. Technical Know-How Needed - Good hands-on experience of System Verilog & uVM (Universal Verification Methodology) - Capable of developing ...
Key Skills : System Verilog,UVM,Verilog HDL,Functional Coverage,Assertions
RS 10,00,000 To 20,00,000 p.a. Noida
Looking for a Senior Engineer with 5-8 years of experience in digital design verification domain. Technical Know-How Needed - Good hands-on experience of System Verilog & uVM (Universal Verification Methodology) - Capable of developing ...
Key Skills : System Verilog,uVM,Verilog,Formal Verification
RS 4,00,000 To 15,00,000 p.a. Bangalore
Hiring for Verification Engineer : Skills: BE/B.Tech/ME/M.Tech/MCA Experience Range : 2 to 8 years •Strong on System Verilog and Verification Methodologies such as UVM/VMM/OVM. •Capable of independently defining test plans, develo...
Key Skills : USB,Verification Engineer,System Verilog and Verification Methodologies
RS Up To 50000 Bangalore
The company has proven experts in Internet Of Thing(IoT) and Software Development end to end. Our business philosophy is to achieve excellence in providing design and software services & solutions to our clients to build next generation leadership p...
Key Skills : VLSI Engineer,System Verilog,VHDL,Embedded Systems Programmer,Internet of things
RS 7,00,000 To 12,00,000 p.a. Bangalore
Must have very good System Verilog/UVM knowledge with prior work experience on live projects Expertise in AMBA bus protocols and ARM CPU Experience in developing functional verification environments including the components like monitors, check...
Key Skills : System Verilog,UVM knowledge,AMBA bus protocols,ARM CPU
RS 1,75,000 To 2,75,000 p.a. Bangalore
N Depth Knowledge Of System Verilog And Verification Methodologies Like Ovm, Uvm ·Working Experience On The Uart, Pcie, Avalon Interface, Axi, Fpga Environment ·Working Knowledge Of Modern Pc Architecture; Specific Io Architecture Knowledge A...
Key Skills : HVLs like system Verilog,OVM,UVM,Extensive knowledge of System Verilog and working knowledge of
RS 1,50,000 To 5,00,000 p.a. Hyderabad
Work Location Hyderabad Experience 2 - 10 years Verification Engineer with 2-10 years of relevant experience in HVLs like SystemVerilog/SystemC and methodologies like UVM/OVM/VMM. Candidate should have excel...
Key Skills : ASIC Engineer,PCI,AMBA,AXI,AHB,APB,UVM,OVM,VMM,HVL,system verilog
RS 7,00,000 To 12,00,000 p.a. Bangalore
Job Title: Asic /SOC verification Engineer. Experience: 5 – 7 Years Job Location: Bangalore Job Description: In this role, a Senior Verification Consultant will be involved in verifying SoC and signal processing chipsets with integr...
Key Skills : uvm,System Verilog
RS 2,00,000 To 3,00,000 p.a. Mumbai
VLSI Design Engineers has a training program for 6 - 9 months and work in Design, Modeling, Verification, FPGA Validation, and Product Validation for IPs, FPGAs, ASICs and SOCs as well as EDA Products working in areas of Verilog, SystemVerilog and V...
Key Skills : Logic Design,HDL,RTL,VHDL,Verilog,System Verilog,Verification Engineer
RS 4,00,000 To 6,00,000 p.a. Bangalore
SoC or IP Experience - Languages: System Verilog - DDR/USB/Ethernet/PCIE/Video
Key Skills : system verilog
RS 1,00,000 To 3,00,000 p.a. Bangalore
DV Engineers having experience in (System Verilog, UVM) Experience 3 Years to 8 Years Job Locations Bangalore, Shanghai, JD:- a ) SoC based verification: - Must have working knowledge of Verilog , System Verilog (HVL)
Key Skills : System Verilog,UVM,OVM,AXI,ACE,AHB,APB,VERILOG,AMBA
RS 1,00,000 To 3,00,000 p.a. Hyderabad, Secunderabad
- Engineer Will Be Responsible for Designing the Asic to Meet the Specifications Defined. - Responsible for Defining and Implementing Micro-architecture Design and Development of Various Functional Blocks. - Responsible for Design of Soc-level Log...
Key Skills : SOC Design,ASIC Design,RTL Design,DFT System Verilog