System Verilog Jobs

VLSI Systems Faculty Immediate Hiring Job Opportunity:Walk-In Interview for VLSI Engineer (Trainer)Date: 13th September 2025Time: 11:00 AM 2:00 PmBE/B.Tech/ME/M.Tech/BSc/MSc in ECE, EEE, or EIECandidates from Anna University, Tamil Nadu preferredFreshers and experienced candidates welcomeMinimum 70% in graduation and at least 65% in 10th and 12thJob Role:Train fresh engineering graduates in VLSITeach VLSI programming and practical projectsWork on R&D, prototypes, and industry projectsLearn new tech like AI/ML and advanced Embedded SystemsGuide students for their career in VLSISkills Needed:Positive attitude and good academicsGood communicationWillingness to learn new technologiesInterest in FPGA, ASIC, SoC, Verilog, RTL, SystemVerilog, UVMSalary (3-year contract):18,000/month starting4,000 increase after each yearAbout MIET:MIET is a training institute specializing in embedded systems, helping freshers start careers since 2011.Interview Location:Mirror Institute For Embedded Technology184/2, 3rd Floor, Chandamama Building,Arcot Rd, Vadapalani, Chennai 600026(Opposite Kamala Theater, Upstairs to Viveks Showroom)Website: www.lastbenchindia.comContact: 93809 48474Only eligible and interested candidates should attend.

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A broad career platform- Cross regional and multi business development opportunities, equal achievement for everyone. A free working atmosphere- Flexible working hours and equal communication mechanism. Superior work benefits- Rich rewards and competitive remunerationIf this is a journey youd like to embark on, keep reading!In this position you will:The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.Requirements:-Bachelor Degree or M.S. in Electrical Engineering or Microelectronics.-5y & above exp with pre-silicon UVM experienceThe candidate should have good understanding on ASIC/SOC design flow and should have: 1. Strong coding with Verilog and SystemVerilog2. Good knowledge of design verification methodology UVM.3. Many experiences with sequence creation, functional cover groups and assertion coding.4. Strong C/C++ software development experiences5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby.

Hiring for 31 Information Technology Architect Jobs in Shimla,Patna,Bengaluru,Kohima,Chennai,Bhuleshwar, Mumbai,Jaipur,Padri Bazar, Gorakhpur,Visakhapatnam,Baloda Bazar, for Freshers,Required Educational Qualification is : B.A, B.C.A, B.Com, B.Ed, B.Sc, B.E, B.Tech, MBBS, Post Graduate Diploma, M.Sc with Good knowledge in Problem Solving,Communication,Web Analyzer,System Verilog,E-commerce,Marketing,Branch Sales,Time Management etc.

1. 4 to 6 Years of Experience.2. Strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology3. Experience on development of Testbench from scratch and knowledge of DUT integration with verification environment.4. Good knowledge of various EDA tools (Cadence/Synopsys/Mentor)5. Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI 6. Good knowledge of scripting languages like shell/perl/python/Makefile etc.

Hello VLSI Professionals!!!We are hiring below positions:*Physical Design Engineer*Physical Verification Engineer*RTL Design Engineer*Design & verification Engineer*FPGA Design Engineer*DFT Engineer*Emulation Engineer*STA & SynthesisExperience Level : 3+ Years in relevance. (Freshers can also apply for Intern)Notice Period : Immediate-60 days.Work Location : Bangalore, Hyderabad and Chennai**Selected candidates will receive call letter for Technical rounds**VLSI design has a promising future with several exciting trends and technologies emerging in the field. One of the key trends is the integration of System-on-Chip (SoC), which involves combining multiple functionalities onto a single chip. This integration enables higher performance, increased power efficiency, and reduced form factors for electronic devices.Another noteworthy trend is the continuous scaling down of transistor dimensions, which has been the driving force behind the historical growth of IC computing power. Shrinking transistor dimensions allows for increased transistor density and improved device performance. However, as transistor sizes approach their physical limits, alternative design and manufacturing techniques such as nanoscale technologies and 3D integration are being explored to further enhance the capabilities of VLSI systems.Additionally, VLSI design is closely tied with related fields such as artificial intelligence (AI) and Internet of Things (IoT). The growing demand for AI and IoT applications is pushing the development of VLSI systems that can support the processing and connectivity requirements of these technologies.

Work Location: Bangalore / Hyderabad / Coimbatore. EXP- 5+Design Verification - Strong UVM/SV- IP and SOC DV- AXI- 5+ need to have strong protocol Exp such as DDR. PCIe, EthernetDesign Verification - Gate Level Simulations (GLS)- Gate Level Simulation (GLS) knowledge is must- IP and SOC DV- 5+ need to have strong GLS expRTL Design - NO FPGA engineers. They shall have worked on ASIC flow- Keywords - SPYGLASS, LEC, LINT, Synthesis,Emulation - UVM/SV- Synopsys Zebu- Transactor development OR running design with Firmware on ZebuFORMAL - Design Verification - Strong UVM/SV- Experience on Cadence Jasper Gold or Incisive formal verifier (IFV)- Connectivity Check, Register Validation etc.- 7+ need to have some protocol

About Company :SiMa is a machine learning company transforming the embedded edge market through high-performance compute at the lowest power. Initially focused on computer vision applications, the company's software-first approach simplifies ML integration and supports the broadest set of capabilities through a purpose-built MLSoC platform, enabling rapid adoption and creating the best of ease-of-use experience. SiMa.ai is led by technologists and business veterans and backed by a set of top investors committed to helping customers scale machine learning at the edge. For more informationJob Description :- As the Hardware Design Verification Engineer, you will help lead and develop the verification methodology for SiMa.ai's MLSoC- .- As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support.- You will work very closely with the Architecture, RTL/uArch, and cross-functional teams.Areas of focus :Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team.Minimum Qualifications :- BS in Computer Science/EE with 15+ years of experience or MS in Computer Science/EE with 12+ years of experience in HW Design Verification.- Experience with block level, cluster level or chip/SoC level verification.- Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, System Verilog.- Expertise in scripting languages, python or perl.- Strong experience in helping emulation and validation.- Experience with modeling various HW blocks, IPs for verification, emulation.- Ability to analyze systems-level performance, profiling, and analysis.

IP verification Using SV/UVM SOC Verification using C/SV Third Party VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (3+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+) Memory Interfaces: DDR or HBM I/O (10+) Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incsive Technical Documentation: Testbench Specification, Test Plan Specification Foundry Porting Experience: Technology Library Conversion Related Changes Verification

Required VLSI dsign engineers in DV, PD, DFT, Analog layout. Interested candidates send your resume

Job descriptionThe candidate will have a key role in architecture and development of advanced verification environments for complex SoC components, while ensuring on time, one time best-in-class quality. The candidate will have a significant opportunity to interact with system design teams across geographies.Job Requirements An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans Analog mixed signal experience and analog modeling is a strong plus. Relevant experience with one or more of PCIe, NVMe, NAND, DDR, and CPU sub-systems. Work experience in I2C, USB 3.0, AXI, PCIe, SPI, Ethernet etc. desired Deep understanding and knowledge of verification methodologies, flows and quality metrics. Great debugging and problem-solving skills Work closely with designers to resolve bugs Team player with great interpersonal communication skills. Having an entrepreneur's spirit for growing business an added plusJob Qualifications 5-10+ years relevant experience in SoC verification. 1-2 years experience in leading a small team an added plus Strong and relevant expertise with ASIC simulation tools and advanced verification methods. Expert level in verification languages such as UVM and System Verilog. Relevant experience with writing block-level and SoC test-plans Scripting experience (Python/ Perl/ Tcl) a big plus

Experienced in Design Verification minimum 2 Years

We required total 3 candidates for hardware engineer in which:-2candidate- of 1-2yrs experienced1candidate of 3-4yrs experiencedThe CTC we are offering is:-1yr experienced -up to 4lpa2yrs experience-up to 8lpa3yrs- experienced -upto12lpa4-yrs-experienced -up to 15lpa> Location: Delhi>> Job Title: Hardware Engineer>> Available Posts: 2 - 3 (Vacancies)>> JOB DESCRIPTION>> * - Knowledge of FPGA programming from requirements till validation> - Knowledge in Verilog / System Verilog / VHDL>> * Salary:1LPA -15LPA>> Role Category: Programming & Design>> Role: Hardware Design Engineer / Programmer Analyst>> KEYSKILLS>> FPGA> Xilinx> Programming (C/C++)> validation>> * o Knowledge in FPGA/ASIC based design and verification.> o Expertise in C programming.> o Design in VHDL, Verilog and System Verilog.> o Knowledge in working with Xilinx IDE/tool chain (ISE/Vivado)>> Experience: 1 - 4 years>> Working Hours: 9 hrs/day> Working Days: 6 days/week, Sundays are off.

Hi,Greetings from SkandysysWe are currently hiring potential DFT Engineers, who are having 3+ years experience for our substantial ongoing and upcoming projects. Job location would be BangaloreGood practical exposure in the following list: Scan, Compression logic Insertion & DRC Cleaning MBIST Insertion & Verification The remuneration and perks are unmatchable in the market.Waiting for your positive outlook.

We have vacant of 90 Design verification Engineer Jobs in Bangalore,Hyderabad,Noida,Chennai Experience Required : 3 Years Educational Qualification : B.Tech/B.E, M.Tech Skill UVM,System Verilog,AXI,AHB,Debug etc.