Verification Engineer Graduate Jobs in Bangalore

Responsibilities:Lead end-to-end verification from complex CPU sub-units up to CPU clusters, partnering with architecture and design teamsDevelop verification infrastructure components including test-benches, scoreboards, and stimulus generatorsDevelop and execute comprehensive verification plans for units and featuresImplement functional coverage modelsDebug designs in simulation, prototyping platforms, and siliconContinuously drive methodology improvements to improve efficiencyLead senior and junior engineers as a team to accomplish successful projectsMinimum Qualifications: Bachelors or Masters degree in electrical, computer engineering or related fieldBS+10 years or MS+12 years of industry experience successfully delivering CPU implementationsSkills & Qualifications Required: System Verilog verification development experienceTest bench construction using UVM or analogous methodologiesScoreboards and stimulus generators for complex unitsStrong background in one or more common CPU ISAs. x86, ARM, MIPS, RISC-V, etc.Strong background in processor coherency and MP programmingProject ownership throughout the project lifecycle Demonstrated team leadership experience with outstanding communication skills Highly motivated self-starter with strong execution mindset and collaborative approachPost-silicon debug experience strongly preferred

Design and Develop Embedded Software (Low Level Driver) for multicore Controller, Safety and Security modules Analyze Software and System Requirements in line with AUTOSAR Spec Participation in customer meetings for requirement clarification Derive Verification and Validation criteria for Requirements Derive the simulation software requirements based on the validation scope and approach Configure base Software components in accordance with customer specific requirement AUTOSAR sw component integration and RTE Configurations Perform SW Safety Analysis as per ISO26262 Support in task estimations, technical reviews, technical clarifications, problem analysis discussions Willing to travel to customer site @Europe on business need

JD:Location:Bangalore/HyderabadExp:4+ Previously developed packet based test bench using UVM verification methodologyExperience in creating and maintaining block level test benches and converting them for top level usageExperience in random and directed test methods, coverage analysis (code coverage and functional coverage) and score boardingStrong System Verilog coding skillsUnderstanding of ASIC design and hands on RTL coding skillsExperience with high speed and network interfaces Expertise in Any one of the Protocols : Ethernet MAC and IP transport, PCIE, USB, DDR, MIPI, HDMI.SOC architectures, high speed interconnect buses such as AHB, APB and interfaces such as SERDES, I2C, Exposure to communications/DSP building blocks and/or SOC functional modulesRequired ExperienceStrong logical and creative problem-solving skills with excellent analytical and debugging skillsMust be a flexible self-starter who can ramp up with new technologies, products, etc.Motivated, and able to work effectively under pressureGood written and oral communication skills

About Company :SiMa is a machine learning company transforming the embedded edge market through high-performance compute at the lowest power. Initially focused on computer vision applications, the company's software-first approach simplifies ML integration and supports the broadest set of capabilities through a purpose-built MLSoC platform, enabling rapid adoption and creating the best of ease-of-use experience. SiMa.ai is led by technologists and business veterans and backed by a set of top investors committed to helping customers scale machine learning at the edge. For more informationJob Description :- As the Hardware Design Verification Engineer, you will help lead and develop the verification methodology for SiMa.ai's MLSoC- .- As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support.- You will work very closely with the Architecture, RTL/uArch, and cross-functional teams.Areas of focus :Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team.Minimum Qualifications :- BS in Computer Science/EE with 15+ years of experience or MS in Computer Science/EE with 12+ years of experience in HW Design Verification.- Experience with block level, cluster level or chip/SoC level verification.- Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, System Verilog.- Expertise in scripting languages, python or perl.- Strong experience in helping emulation and validation.- Experience with modeling various HW blocks, IPs for verification, emulation.- Ability to analyze systems-level performance, profiling, and analysis.

Hiring Now!VLSI EngineerAnalog layoutExperience 4+yearsLocation: Bangalore

We have vacant of 90 Design verification Engineer Jobs in Bangalore,Hyderabad,Noida,Chennai Experience Required : 3 Years Educational Qualification : B.Tech/B.E, M.Tech Skill UVM,System Verilog,AXI,AHB,Debug etc.

Required VLSI dsign engineers in DV, PD, DFT, Analog layout. Interested candidates send your resume

Greetings from Mindtekwe have requirement for Lead and soc verification and Pd engineers for one of the large semiconductor company in bangalore. Interested candidates share your cv.

Experienced in Design Verification minimum 2 Years

SV, UVM, USB, DDR, PCIE, Ethernet, Axi, MIPI. Any one of the protocols will be addedadvantage. Experience in verification of complex IPs or SoCs. Expertise in SoC Verification using C and SV/UVM.Expertise in AMBA protocols AXI/AHB/APB and experience in working with ARM Processors. Expertise in Test Plan creation and Verification technologies like Code Coverage, FunctionalCoverage and Assertions.