JD:
Location:Bangalore/Hyderabad
Exp:4+
Previously developed packet based test bench using UVM verification methodology
Experience in creating and maintaining block level test benches and converting them for top level usage
Experience in random and directed test methods, coverage analysis (code coverage and functional coverage) and score boarding
Strong System Verilog coding skills
Understanding of ASIC design and hands on RTL coding skills
Experience with high speed and network interfaces
Expertise in Any one of the Protocols : Ethernet MAC and IP transport, PCIE, USB, DDR, MIPI, HDMI.
SOC architectures, high speed interconnect buses such as AHB, APB and interfaces such as SERDES, I2C,
Exposure to communications/DSP building blocks and/or SOC functional modules
Required Experience
Strong logical and creative problem-solving skills with excellent analytical and debugging skills
Must be a flexible self-starter who can ramp up with new technologies, products, etc.
Motivated, and able to work effectively under pressure
Good written and oral communication skills