RS 5,00,000 To 8,00,000 p.a. Bangalore
Preferred skills : -RTL design experience, familiarity with AHB/AXI buses, experience with spyglass(lint), CDC, core and chip integration.
Key Skills : RTL design engineer
RS 5,00,000 To 13,00,000 p.a. Bangalore
• Develop micro-architecture and RTL implementation. • Block level/ full chip integration and design. • Hands-on with Lint, CDC , LEC and preferably Low Power check tools • Some experience of AXI/AHB • design in System Verilog and timin...
Key Skills : ASIC Synthesis,ASIC Design,lint,cdc,Synthesis,Verilog,ovm,uvm,RTL,Verification Engineer,RTL design
RS 1,00,000 To 4,00,000 p.a. Hyderabad
The Design and Verification Engineer will be core technical individual contributor in designing and verifying IPs used in SoCs of IMGWorks.
Key Skills : design verification,design engineering,rtl coding,rtl design engineer,rtl design
RS 6,50,000 To 12,00,000 p.a. Bangalore
Job title: DFT Engineer Years of Exp: 3 - 4 Years Job Description: •Team Lead exposure and taking ownership of design deliverance •Primary responsibilities will include driving the DFT implementation and verification ....
Key Skills : DFT,MBIST,RTL,ATPG,TDF
RS 2,25,000 To 5,00,000 p.a. Bangalore
Expertise in RTL Verification * Verification of RTL using SV, OVM/UVM * Experience in verification environment development * Verification of gate level netlist using OVM/UVM testbenches * Expertise in standard protocols * Experience in...
Key Skills : Verification Engineer,RTL Verification,Chip Level Verification,Verification Engineering
RS 2,00,000 To 3,00,000 p.a. Mumbai
VLSI Design Engineers has a training program for 6 - 9 months and work in Design, Modeling, Verification, FPGA Validation, and Product Validation for IPs, FPGAs, ASICs and SOCs as well as EDA Products working in areas of Verilog, SystemVerilog and V...
Key Skills : Logic Design,HDL,RTL,VHDL,Verilog,System Verilog,Verification Engineer
RS 1,00,000 To 3,00,000 p.a. Hyderabad, Secunderabad
- Engineer Will Be Responsible for Designing the Asic to Meet the Specifications Defined. - Responsible for Defining and Implementing Micro-architecture Design and Development of Various Functional Blocks. - Responsible for Design of Soc-level Log...
Key Skills : SOC Design,ASIC Design,RTL Design,DFT System Verilog