RTL Jobs

We are seeking experienced DFT Engineers with expertise in Scan, ATPG, and MBIST for SoC / ASIC designs. This role focuses on implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness. Key ResponsibilitiesImplement and verify Scan, ATPG, and MBIST for complex SoCs.Perform pattern generation, coverage analysis, and debug.Integrate and validate MBIST with memory test algorithms.Collaborate with RTL and Physical Design teams for smooth DFT integration and sign-off.Develop automation scripts to streamline DFT flows. Required Skills4 to 10 years of DFT experience in ASIC / SoC environments. (Rs 22L to Rs 28L per annum)Hands-on expertise with EDA tools:Synopsys (DFT Compiler, TestMAX, TetraMAX)Cadence ModusPreferred: Siemens Tessent / FastScanStrong understanding of fault models (stuck-at, transition, path delay).Knowledge of MBIST architecture and memory test techniques.Scripting skills in TCL, Perl, Python.Familiarity with RTL design flows, STA constraints, and silicon bring-up.Send your resumes to mstechtalentacq@gmail.com and we will contact you.

VLSI Systems Faculty Immediate Hiring Job Opportunity:Walk-In Interview for VLSI Engineer (Trainer)Date: 13th September 2025Time: 11:00 AM 2:00 PmBE/B.Tech/ME/M.Tech/BSc/MSc in ECE, EEE, or EIECandidates from Anna University, Tamil Nadu preferredFreshers and experienced candidates welcomeMinimum 70% in graduation and at least 65% in 10th and 12thJob Role:Train fresh engineering graduates in VLSITeach VLSI programming and practical projectsWork on R&D, prototypes, and industry projectsLearn new tech like AI/ML and advanced Embedded SystemsGuide students for their career in VLSISkills Needed:Positive attitude and good academicsGood communicationWillingness to learn new technologiesInterest in FPGA, ASIC, SoC, Verilog, RTL, SystemVerilog, UVMSalary (3-year contract):18,000/month starting4,000 increase after each yearAbout MIET:MIET is a training institute specializing in embedded systems, helping freshers start careers since 2011.Interview Location:Mirror Institute For Embedded Technology184/2, 3rd Floor, Chandamama Building,Arcot Rd, Vadapalani, Chennai 600026(Opposite Kamala Theater, Upstairs to Viveks Showroom)Website: www.lastbenchindia.comContact: 93809 48474Only eligible and interested candidates should attend.

Openings for Medical coder Radiology/Certified coderAny Graduation Experience 4 to 9year Location Chennai Skills Certified coder, Diagnostics radiology, IVR coder, Ancillary codingSalary -Business standard Day/Night shift Working days 5 days in a Week Required Candidate profile:Looking for any certified coder with radiology specialty Preferred Immediate Joiner Interested candidate Contact HR9840895957

This role is an exciting opportunity for a ASIC designer to contribute in a team of highly skilled design engineers within the SouthBridge IO (SBIO) team. Provide IP technical management and support for the end-to-end design development flow. This includes from architecture, microarchitecture, RTL design, design metrics (performance, power, area) analysis and design for verification strategy. Collaborate with design and verification teams to ensure a predictable IP development. Exhibits relentless commitment to help the team meet quality and development goals on schedule Drives to learn and perform at his or her highest potential in a technical capacity Thrives in both a team environment and in individual contribution Communicates openly and clearly in meetings, presentations, emails, and reports Able to learn independently and acquire new skills required for the job Creative and innovator and thinker who loves technical problems and detail-oriented tasksKEY RESPONSIBLITIES: IP RTL design for USB IP used for all next generation server, clients, GPU and Semicustom products. Work closely with IP and system architects to micro-architect cutting edge features. Apply low power design techniques to existing logic and maintain overall systemperformance. Focus on timing, LINT and CDC closure to ensure high quality RTL. Support verification and debug of the ASIC throughout various stages of the project. Jump into the lab and solve post silicon bring-up or customer issues. Analyzecomplex digital design problems and propose solutions. Develop Verilog RTL and Functional Behavioral Models. Drive/develop ASIC design flows and scripts. Create microarchitecture specifications. Work with Design Verification team to ensure functional correctness. Work with Physical Design team to ensure proper implementation of the design along with timing closure. Deliver improvements, optimization and power saving enhancements. At least 4 years experience

1.HDL-verilog,VHDL,TOOLS-intel quartus-2,xilinx vivado and xilinx vitis IDE,DEBUGGERS-xilinx J-tag tools,intel quartus-2 debugger,TESTBENCH SKILLS-system verilog and other methodologies ,RTL design as per RTL life cycle,design,development ,test etc ,problem solving with hardware designs,troubleshoot /debug hardwaredesign/board problems.

1. Brining up Linux environment on ARM2. Work will involve interfacing with a camera, display, and some image processing.3. Design implementation (FPGA design and simulation)4. Rapid prototyping, bring up and debug5. Comfortable in Linux environment.Note: Self-motivated, goal oriented and good analytical skills

RTL(Verilog) and SV/UVM Concept and Practical knowledge / Regression using Venus & Granite setup/ Coverage/ UPF/Latency/PerformanceProtocol Knowledge DDR5/EMMC/USB/GBE/AXI4/APB/AHB/DFTKnowledge on Venus & Granite setup and Coverage/ UPF/Latency/PerformanceEmulation expertise in zebu platform and SimicsExperience in C/C++ and scripting tcl/perlBackground in FPGA/SOC design and Verification

JD:Worked on RTL coding on ASIC chips Microarchitecture of the Design Multiple projects on Processor / Automotives / Memory protocolsWorked on Synthesis and STA design flow Good hold on Linting / spyglass CDC Handled team and good team leading skillsWorked on PCIE / DDR / USB protocols

Work Location: Bangalore / Hyderabad / Coimbatore. EXP- 5+Design Verification - Strong UVM/SV- IP and SOC DV- AXI- 5+ need to have strong protocol Exp such as DDR. PCIe, EthernetDesign Verification - Gate Level Simulations (GLS)- Gate Level Simulation (GLS) knowledge is must- IP and SOC DV- 5+ need to have strong GLS expRTL Design - NO FPGA engineers. They shall have worked on ASIC flow- Keywords - SPYGLASS, LEC, LINT, Synthesis,Emulation - UVM/SV- Synopsys Zebu- Transactor development OR running design with Firmware on ZebuFORMAL - Design Verification - Strong UVM/SV- Experience on Cadence Jasper Gold or Incisive formal verifier (IFV)- Connectivity Check, Register Validation etc.- 7+ need to have some protocol

Open Positions: RTL DESIGN EngineerEducation: M.Tech (2022, 2021,2020,2019,2018 .........)B.Tech (2020, 2019,2018,2017...........)Skills Required: Strong in Digital Electronics & Verilog.Knowledge in LINT, CDC, Spyglass would be an added advantage.Experience: 0-4 YearsLocation: Hyderabad / BangaloreAvailability: Immediate

Key Qualification 4+ years of experience with large FPGA development on Xilinx / Altera/ Microsemi Devices 4+ years of RTL development using Verilog / VHDL/ System-Verilog/UVM /C/C++ Well versed with FPGA design flow including design entry, synthesis, Implementation, place and route, timing constraints and timing closure In-depth background in HDL development, Verilog coding, integration, synthesis, debug, simulation, test bench creation Experienced with test planning, test bench architecture and assertions Constrained random verification experience with SystemVerilog and UVM Coverage driven verification (code/functional/assertion coverage) Demonstrated experience working on FPGA design projects, including work with SoC (ARM/RISC-V CPU), 10/ 40/ 100G Ethernet PHY, DDR#, PCI-E, SDIO interfaces. Hands on experience with lab debug equipment, such as oscilloscopes, logic analyzers, soldering Effectively communicate with cross functional team for bringing up designs Good knowledge with high speed bus protocols including AMBA/AXI3/AXI4 and low speed protocols including USB / SPI / UART/ IIC and other native protocols Experienced with ADC / DAC / EEPROM and other peripheral componentsPreferred Experience with SERDES / JESD204B /Gb PHY is PLUS Ability to communicate and work well with team Excellent interpersonal skills and self-motivation Ability to work well in a team and be productive under tight schedules Knowledge of computer architecture is plus Excellent written and verbal communication skills PCB-Schematic Reading Full Design Integration and debug Good understanding of low-level software and device drivers such as Firmware, Boot.

Required VLSI dsign engineers in DV, PD, DFT, Analog layout. Interested candidates send your resume

Hands-on in Verilog/ VHDL Hands-on in Perl/ Unix scripting Hands on in SoC level RTL integration Hands on in Clock Domain Crossing (CDC) checks, Linting, equivalence checks Experience in Digital module micro-architecture and design Experience in basic RTL simulation IP generation enhancement kind of work Good knowledge of Synthesis, STA and DFT aware design. Good knowledge of ARM subsystem, I2C protocol, AMBA bus Understanding of Power Domains and low power design techniques Familiar with DSP subsystems and high speed interfaces(e.g. SERDES, GigE, 10GE) Ability to lead & motivate a team of Engineers

Fresh Graduates who have completed M.E/M.Tech/M.S./Ph.D in ECE/VLSI/Microelectronics.Vacancy in Domains : Circuit Designing, Layout Designing RTL, Physical Design