Talent Zone Consultant
RS Not disclosed Bangalore
Working Experience with Standard Protocols such as Usb, Pcie, Ethernet, Mipi, Ddr. must have Experience with Ip Level and Soc Level Verification with Test Plan Development, Test Bench Coding must have Strong Background in Logic Verifica...
Key Skills : Design Verification Engineer
Global Talent Pool
RS 5,00,000 To 15,00,000 p.a. Bangalore
Experience in Design Verification. oexperience Developing and Working with Object Oriented Verification Languages (vera, Specman, System Verilog, Vmm, Ovm, Uvm) oa Solid Understanding of Object-oriented Concepts and Experience Designing...
Key Skills : Verification Engineering,Design engineering,c++,Perl,Verilog,Vmm
RS Not disclosed Hyderabad, Bangalore
Location :- Bengaluru / Hyderabad No. Of Positions - 2 Experience:- RTL Design 2+ Years IP Verification 2+ Years IP Design/ SOC Design 4+ Years FPGA Design 6+ Years Job Description: Independent In-charge of the FPGA D...
Key Skills : RTL Coding,IP veification,IP Design,Soc design,FPGA Design,mipi,ODR,DDR2
Global Talent Pool
RS 6,00,000 To 15,00,000 p.a. Bangalore
knowledge with prior work experience on live projects. Expertise in creating detailed test plan with well-defined functional coverage. • Should be able to architect and implement self generating / self checking simulation verificati...
Key Skills : uvm,sv,design verification engineer,design engineer
RS 1,50,000 To 4,25,000 p.a. Bangalore, Kochi, Pune, Noida
• You will be part of the team verifying IPs and SoCs leading to first Si success. • IP verification is coverage driven using latest industry standard methodologies and HVLs. • Work involves defining verification strategy, writing test pl...
Key Skills : Design Engineer,C,C++
RS 50,000 To 15,00,000 p.a. Hyderabad, Bangalore
Design Verification • Very good system Verilog /UVM/OVM knowledge with prior work experience on live projects • Good logical thinking and excellent at solving the digital logic • Must have hands on experience in complete IP/SoC Verific...
Key Skills : uvm,syetemverilog,asic designing,design,design verification
RS 5,00,000 To 13,00,000 p.a. Bangalore
• Develop micro-architecture and RTL implementation. • Block level/ full chip integration and design. • Hands-on with Lint, CDC , LEC and preferably Low Power check tools • Some experience of AXI/AHB • design in System Verilog and timin...
Key Skills : ASIC Synthesis,ASIC Design,lint,cdc,Synthesis,Verilog,ovm,uvm,RTL,Verification Engineer,RTL design