Thundersoft

Malaysia

A broad career platform- Cross regional and multi business development opportunities, equal achievement for everyone. A free working atmosphere- Flexible working hours and equal communication mechanism. Superior work benefits- Rich rewards and competitive remunerationIf this is a journey youd like to embark on, keep reading!In this position you will:The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.Requirements:-Bachelor Degree or M.S. in Electrical Engineering or Microelectronics.-5y & above exp with pre-silicon UVM experienceThe candidate should have good understanding on ASIC/SOC design flow and should have: 1. Strong coding with Verilog and SystemVerilog2. Good knowledge of design verification methodology UVM.3. Many experiences with sequence creation, functional cover groups and assertion coding.4. Strong C/C++ software development experiences5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby.

Collaborate with design, validation, and architecture teams for IP content coverage, test pattern and test program development, validation, and debugDevelop test program infrastructure incorporating latest Best-Known MethodsValidate new product features, test conditions, test methodologies, and test contents during first silicon bring-upPerform silicon characterization across process, voltage, and temperaturePerform test program correlation and release for high volume productionDrive Key Performance Indicators such as test time reduction, yield debug, and quality improvement across productsSupport qualification activities and customer return debugRequirements:More than 4 years of experience in semiconductor product developmentExperience with ATE test program and pattern development Advantest 93K, a must.HBM, Scan, Bist and test program integrations experiences.Proficient in software programming and scripting languages (C, C++, Java, Ruby, Perl, Python)Knowledgeable in version control tools (Git, SVN, CVS)Knowledgeable in statistical analysisProficient in Windows, Unix, and Linux operating systemsStrong written and verbal communication skills

This role is an exciting opportunity for a ASIC designer to contribute in a team of highly skilled design engineers within the SouthBridge IO (SBIO) team. Provide IP technical management and support for the end-to-end design development flow. This includes from architecture, microarchitecture, RTL design, design metrics (performance, power, area) analysis and design for verification strategy. Collaborate with design and verification teams to ensure a predictable IP development. Exhibits relentless commitment to help the team meet quality and development goals on schedule Drives to learn and perform at his or her highest potential in a technical capacity Thrives in both a team environment and in individual contribution Communicates openly and clearly in meetings, presentations, emails, and reports Able to learn independently and acquire new skills required for the job Creative and innovator and thinker who loves technical problems and detail-oriented tasksKEY RESPONSIBLITIES: IP RTL design for USB IP used for all next generation server, clients, GPU and Semicustom products. Work closely with IP and system architects to micro-architect cutting edge features. Apply low power design techniques to existing logic and maintain overall systemperformance. Focus on timing, LINT and CDC closure to ensure high quality RTL. Support verification and debug of the ASIC throughout various stages of the project. Jump into the lab and solve post silicon bring-up or customer issues. Analyzecomplex digital design problems and propose solutions. Develop Verilog RTL and Functional Behavioral Models. Drive/develop ASIC design flows and scripts. Create microarchitecture specifications. Work with Design Verification team to ensure functional correctness. Work with Physical Design team to ensure proper implementation of the design along with timing closure. Deliver improvements, optimization and power saving enhancements. At least 4 years experience