Terra EE Source Infotech LLP

Ganganagar, Bangalore

JD:Location:Bangalore/HyderabadExp:4+ Previously developed packet based test bench using UVM verification methodologyExperience in creating and maintaining block level test benches and converting them for top level usageExperience in random and directed test methods, coverage analysis (code coverage and functional coverage) and score boardingStrong System Verilog coding skillsUnderstanding of ASIC design and hands on RTL coding skillsExperience with high speed and network interfaces Expertise in Any one of the Protocols : Ethernet MAC and IP transport, PCIE, USB, DDR, MIPI, HDMI.SOC architectures, high speed interconnect buses such as AHB, APB and interfaces such as SERDES, I2C, Exposure to communications/DSP building blocks and/or SOC functional modulesRequired ExperienceStrong logical and creative problem-solving skills with excellent analytical and debugging skillsMust be a flexible self-starter who can ramp up with new technologies, products, etc.Motivated, and able to work effectively under pressureGood written and oral communication skills

JD:Worked on RTL coding on ASIC chips Microarchitecture of the Design Multiple projects on Processor / Automotives / Memory protocolsWorked on Synthesis and STA design flow Good hold on Linting / spyglass CDC Handled team and good team leading skillsWorked on PCIE / DDR / USB protocols

JD:Worked on 14nm / 28nm technology STA / SYN/ IC implementation / CDC / Physical Verification Worked on High speed protocol like DDR / USB/ PCIE Implementation is mustStrong hold on technology nodes Flexible and ready to take ownership to complete sign off

JD:Worked on Zebu /Palladium emulation platform worked on maestro / super collider platform good hands on emulation debug and building emulation environentGood knowledge on C/C++ is requiredSV knowledge is added advantageWorked on atleast 2 Soc emulation completely

JD:Worked on DFT / MBIST / Scan cell insertionsWorked on more than million cell count projectworked on Soc DFT verification Good hold on timings and flops Good knowledge MBIST / CBIST/ Scan chain / Boundary scan insertions Good knowledge on Design for debug is added advantage