2

VLSI Design Engineer Graduate Experience Jobs in Hyderabad

Filters

  • 9 - 12 yrs
  • Hyderabad
VLSI Design RTL Design ASIC SOC Verilog SystemVerilog RTL Coding Digital Design Synthesis Simulation STA FPGA Design Verification DFT EDA Tools
Senior VLSI Design Engineer SemiconductorExperience: 9-12 YearsLocation: HyderabadHiring Company: Talent Zone ConsultantBrief JD:We are hiring a Senior VLSI Design Engineer with strong experience in digital IC/SoC design. The role involves RTL design, coding, simulation, debugging, synthesis and working closely with verification and physical design teams.Key Responsibilities:Develop and implement RTL designs for ASIC/SoC projects.Write and debug Verilog/SystemVerilog RTL.Perform simulation, synthesis and design analysis.Debug functional and timing-related issues.Collaborate with verification, DFT and physical design teams.Review design specifications and technical documentation.Relevant Skillset:VLSI Design, RTL Design, ASIC, SoC, Verilog, SystemVerilog, RTL Coding, Digital Design, Synthesis, Simulation, STA, FPGA, Design Verification, DFT, EDA Tools
View all details
  • 5 - 9 yrs
  • 40.0 Lac/Yr
  • Hyderabad
C Language VLSI-Very Large Scale Integration EDA System Verilog ASIC Verification RTL GLS UVM
Work Location: Bangalore / Hyderabad / Coimbatore. EXP- 5+Design Verification - Strong UVM/SV- IP and SOC DV- AXI- 5+ need to have strong protocol Exp such as DDR. PCIe, EthernetDesign Verification - Gate Level Simulations (GLS)- Gate Level Simulation (GLS) knowledge is must- IP and SOC DV- 5+ need to have strong GLS expRTL Design - NO FPGA engineers. They shall have worked on ASIC flow- Keywords - SPYGLASS, LEC, LINT, Synthesis,Emulation - UVM/SV- Synopsys Zebu- Transactor development OR running design with Firmware on ZebuFORMAL - Design Verification - Strong UVM/SV- Experience on Cadence Jasper Gold or Incisive formal verifier (IFV)- Connectivity Check, Register Validation etc.- 7+ need to have some protocol
View all details