6

Verilog Job Vacancies in Hyderabad

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VLSI Design Engineer

AdvanSoft

  • Experience 5 - 9 yrs
  • Salary 40.0 Lac/Yr
  • Location Hyderabad
C LanguageVLSI-Very Large Scale IntegrationEDASystem VerilogASIC VerificationRTLGLSUVM
Apply

Design & Verification SR. Engineer/Lead/Managers ASIC (Design Verification )

Tessolve Semiconductor

UvmSystem VerilogSOCIPPCIEMipiZebuWork From Home
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RTL Design Engineer

Bitsilica Private Limited

VerilogDigital Design
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Design Verification

APAQ Technologies Pvt Ltd

Design VerificationASIC Design Verification EngineerVerilogSystem VerilogPCIE
Apply
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DFT Engineer

SKANDYSYS PVT LTD

System VerilogSynthesisDFT EngineerDRC Cleaning
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Design Verification Engineer

Tessolve Semiconductor Pvt Ltd

UVMSystem VerilogAXIAHBDebugDesign Verification EngineerDesign EngineerWork From Home
Apply