Verilog Jobs in Hyderabad

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Design & Verification Sr. Engineer/Lead/Managers – ASIC (Design Verification )

Tessolve Semiconductor

uvmsystem verilogsocippciemipizebudesign & verification engineer

VLSI Design Engineer

AdvanSoft

  • Experience 5 - 9 yrs
  • Salary Rs.15.0 - 40.0 Lakh/Yr
  • Location Hyderabad
c languagevlsi-very large scale integrationedasystem verilogasic verificationrtlglsuvmvlsic

RTL Design Engineer

Bitsilica Private Limited

verilogdigital designrtl design engineer

Design Verification

APAQ Technologies Pvt Ltd

design verificationasic design verification engineerverilogsystem verilogpcie

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DFT Engineer

SKANDYSYS PVT LTD

system verilogsynthesisdft engineerdrc cleaning

Design verification Engineer

Tessolve Semiconductor Pvt Ltd

uvmsystem verilogaxiahbdebugdesign verification engineerdesign engineer

Embedded FPGA Engineer

OPSIS Consulting

  • Experience 2 - 4 yrs
  • Salary Rs.2.50 - 3.0 Lakh/Yr
  • Location Hyderabad
embedded fpgafpga architecture fpga architecturemodelsimvcsverilog programmingdebuggingxilinx idequesta simhdl designerembedded fpga engineerfpga architecture

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