7

RTL Coding Jobs

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  • 9 - 12 yrs
  • Hyderabad
VLSI Design RTL Design ASIC SOC Verilog SystemVerilog RTL Coding Digital Design Synthesis Simulation STA FPGA Design Verification DFT EDA Tools
Senior VLSI Design Engineer SemiconductorExperience: 9-12 YearsLocation: HyderabadHiring Company: Talent Zone ConsultantBrief JD:We are hiring a Senior VLSI Design Engineer with strong experience in digital IC/SoC design. The role involves RTL design, coding, simulation, debugging, synthesis and working closely with verification and physical design teams.Key Responsibilities:Develop and implement RTL designs for ASIC/SoC projects.Write and debug Verilog/SystemVerilog RTL.Perform simulation, synthesis and design analysis.Debug functional and timing-related issues.Collaborate with verification, DFT and physical design teams.Review design specifications and technical documentation.Relevant Skillset:VLSI Design, RTL Design, ASIC, SoC, Verilog, SystemVerilog, RTL Coding, Digital Design, Synthesis, Simulation, STA, FPGA, Design Verification, DFT, EDA Tools
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Medical Coder

HRCS Private limited

  • 2 - 6 yrs
  • 5.0 Lac/Yr
  • Chennai
RTL Coding Certified Coder Diagnostics Radiology IVR Coder Ancillary Coding
Openings for Medical coder Radiology/Certified coderAny Graduation Experience 4 to 9year Location Chennai Skills Certified coder, Diagnostics radiology, IVR coder, Ancillary codingSalary -Business standard Day/Night shift Working days 5 days in a Week Required Candidate profile:Looking for any certified coder with radiology specialty Preferred Immediate Joiner Interested candidate Contact HR9840895957
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FPGA Design Engineer

Swan Sorter Systems Pvt Ltd

  • 10 - 15 yrs
  • Gottigere Bangalore
Verilog RTL Coding FPGA Design Xilinx ISE Vhdl Intel quartus-2
1.HDL-verilog,VHDL,TOOLS-intel quartus-2,xilinx vivado and xilinx vitis IDE,DEBUGGERS-xilinx J-tag tools,intel quartus-2 debugger,TESTBENCH SKILLS-system verilog and other methodologies ,RTL design as per RTL life cycle,design,development ,test etc ,problem solving with hardware designs,troubleshoot /debug hardwaredesign/board problems.
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  • 3 - 8 yrs
  • Bangalore
Verilog RTL Coding FPGA Design
RTL(Verilog) and SV/UVM Concept and Practical knowledge / Regression using Venus & Granite setup/ Coverage/ UPF/Latency/PerformanceProtocol Knowledge DDR5/EMMC/USB/GBE/AXI4/APB/AHB/DFTKnowledge on Venus & Granite setup and Coverage/ UPF/Latency/PerformanceEmulation expertise in zebu platform and SimicsExperience in C/C++ and scripting tcl/perlBackground in FPGA/SOC design and Verification
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FPGA Design Engineer

Magics Business Solutions

Verilog RTL Coding CPLD ASIC Verification FPGA Design Xilinx ISE RTL Designe
1. Brining up Linux environment on ARM2. Work will involve interfacing with a camera, display, and some image processing.3. Design implementation (FPGA design and simulation)4. Rapid prototyping, bring up and debug5. Comfortable in Linux environment.Note: Self-motivated, goal oriented and good analytical skills
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RTL Engineer

Terra EE Source

RTL Coding
JD:Worked on RTL coding on ASIC chips Microarchitecture of the Design Multiple projects on Processor / Automotives / Memory protocolsWorked on Synthesis and STA design flow Good hold on Linting / spyglass CDC Handled team and good team leading skillsWorked on PCIE / DDR / USB protocols
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FPGA Design Engineer

Motax Solutions Private Limited

  • 4 - 10 yrs
  • Mumbai
Verilog RTL Coding CPLD VLSI Design ASIC Verification FPGA Design Xilinx ISE Emulators RISC VHDL AXI
Key Qualification 4+ years of experience with large FPGA development on Xilinx / Altera/ Microsemi Devices 4+ years of RTL development using Verilog / VHDL/ System-Verilog/UVM /C/C++ Well versed with FPGA design flow including design entry, synthesis, Implementation, place and route, timing constraints and timing closure In-depth background in HDL development, Verilog coding, integration, synthesis, debug, simulation, test bench creation Experienced with test planning, test bench architecture and assertions Constrained random verification experience with SystemVerilog and UVM Coverage driven verification (code/functional/assertion coverage) Demonstrated experience working on FPGA design projects, including work with SoC (ARM/RISC-V CPU), 10/ 40/ 100G Ethernet PHY, DDR#, PCI-E, SDIO interfaces. Hands on experience with lab debug equipment, such as oscilloscopes, logic analyzers, soldering Effectively communicate with cross functional team for bringing up designs Good knowledge with high speed bus protocols including AMBA/AXI3/AXI4 and low speed protocols including USB / SPI / UART/ IIC and other native protocols Experienced with ADC / DAC / EEPROM and other peripheral componentsPreferred Experience with SERDES / JESD204B /Gb PHY is PLUS Ability to communicate and work well with team Excellent interpersonal skills and self-motivation Ability to work well in a team and be productive under tight schedules Knowledge of computer architecture is plus Excellent written and verbal communication skills PCB-Schematic Reading Full Design Integration and debug Good understanding of low-level software and device drivers such as Firmware, Boot.
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