DFT Job Vacancies in Bangalore

We are seeking experienced DFT Engineers with expertise in Scan, ATPG, and MBIST for SoC / ASIC designs. This role focuses on implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness. Key ResponsibilitiesImplement and verify Scan, ATPG, and MBIST for complex SoCs.Perform pattern generation, coverage analysis, and debug.Integrate and validate MBIST with memory test algorithms.Collaborate with RTL and Physical Design teams for smooth DFT integration and sign-off.Develop automation scripts to streamline DFT flows. Required Skills4 to 10 years of DFT experience in ASIC / SoC environments. (Rs 22L to Rs 28L per annum)Hands-on expertise with EDA tools:Synopsys (DFT Compiler, TestMAX, TetraMAX)Cadence ModusPreferred: Siemens Tessent / FastScanStrong understanding of fault models (stuck-at, transition, path delay).Knowledge of MBIST architecture and memory test techniques.Scripting skills in TCL, Perl, Python.Familiarity with RTL design flows, STA constraints, and silicon bring-up.Send your resumes to mstechtalentacq@gmail.com and we will contact you.

Good knowledge of all the DFT concepts & ATPG Flows. Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements. Stuck-At, Transition Delay fault models test pattern generations and Simulations. Expertise in Scan Compression, BSCAN /JTAG and MBIST implementation and verification. Good problem solving and debugging skills. Proactive in nature. Experience in writing scripts in perl/tcl for automation. Sound hands on Experience with industry standard DFT tools & flows(Mentor, Synopsys or Cadence ) Familiarity with Timing constrains development, LEC & Post Silicon ATE Bring-up will be added advantage

Responsibilities Implement DFT including: at-speed scan, LBIST, MBIST, JTAG, self-test, and IP integrationWork closely with synthesis, static timing, and layout engineers to optimize DFT circuits.Generate and verify Test vectors before chip tape out.Support test vector bring up and debug on ATE.Support silicon failure analysis, diagnostics, and yield improvement.Create innovative DFT solutions to solve testability problems and improve coverage.Automate DFT & test vector generation flows.JOB Description (please mention in details) *Deep understanding of DFT concepts such as at-speed scan, LBIST, MBIST, JTAG, self-test, analog DFT, and more.Experience with DFT tools such as Tessent, TetraMax, etc.Scan Insertion and scan compression experience.Memory BIST insertion and verification experience.Logic BIST design and debug experience.Experience with ATPG vector generation, testbench generation, simulation, and debug.Experience with formal equivalence checking (Formality, LEC).Familiar with Verilog and VHDL code.Familiar with IEEE 1149 and 1687.Good understanding of synthesis and static timing principles.Excellent problem solving, debug, and communication skills.Knowledge of analog and digital circuit design, and basic device physics.Able to code using TCL, PERL, PYTHON, C++ or similar.Able to work in a multi-disciplined, cross-department environmentExperience working on ATE is a plus.

JD:Worked on DFT / MBIST / Scan cell insertionsWorked on more than million cell count projectworked on Soc DFT verification Good hold on timings and flops Good knowledge MBIST / CBIST/ Scan chain / Boundary scan insertions Good knowledge on Design for debug is added advantage