ü Good knowledge of all the DFT concepts & ATPG Flows.
ü Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements.
ü Stuck-At, Transition Delay fault models test pattern generations and Simulations.
ü Expertise in Scan Compression, BSCAN /JTAG and MBIST implementation and verification.
ü Good problem solving and debugging skills. Proactive in nature.
ü Experience in writing scripts in perl/tcl for automation.
ü Sound hands on Experience with industry standard DFT tools & flows(Mentor, Synopsys or Cadence )
ü Familiarity with Timing constrains development, LEC & Post Silicon ATE Bring-up will be added advantage
Experience : 4 - 8 Years
No. of Openings : 2
Education : Higher Secondary
Role : Dft Engineer
Industry Type : Manufacturing / Production / Quality
Gender : [ Male / Female ]
Job Country : India