Array ( [0] => dft-engineer [1] => bangalore ) DFT Engineer 12th Pass Fresher Jobs in Bangalore

DFT Engineer 12th Pass Fresher Jobs in Bangalore

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DFT Engineer - Bangalore

Msolvion Technologies

  • 4 - 10 yrs
  • 27.5 Lac/Yr
  • Bangalore
ASIC SOC Environments DFT Compiler TestMAX TetraMAX Tessent FastScan TCL Perl Python RTL STA Constraints
We are seeking experienced DFT Engineers with expertise in Scan, ATPG, and MBIST for SoC / ASIC designs. This role focuses on implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness. Key ResponsibilitiesImplement and verify Scan, ATPG, and MBIST for complex SoCs.Perform pattern generation, coverage analysis, and debug.Integrate and validate MBIST with memory test algorithms.Collaborate with RTL and Physical Design teams for smooth DFT integration and sign-off.Develop automation scripts to streamline DFT flows. Required Skills4 to 10 years of DFT experience in ASIC / SoC environments. (Rs 22L to Rs 28L per annum)Hands-on expertise with EDA tools:Synopsys (DFT Compiler, TestMAX, TetraMAX)Cadence ModusPreferred: Siemens Tessent / FastScanStrong understanding of fault models (stuck-at, transition, path delay).Knowledge of MBIST architecture and memory test techniques.Scripting skills in TCL, Perl, Python.Familiarity with RTL design flows, STA constraints, and silicon bring-up.Send your resumes to mstechtalentacq@gmail.com and we will contact you.
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DFT Engineer

Concord IT Systems

DFT
Good knowledge of all the DFT concepts & ATPG Flows. Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements. Stuck-At, Transition Delay fault models test pattern generations and Simulations. Expertise in Scan Compression, BSCAN /JTAG and MBIST implementation and verification. Good problem solving and debugging skills. Proactive in nature. Experience in writing scripts in perl/tcl for automation. Sound hands on Experience with industry standard DFT tools & flows(Mentor, Synopsys or Cadence ) Familiarity with Timing constrains development, LEC & Post Silicon ATE Bring-up will be added advantage
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DFT Engineer

Terra EE Source

DFT Engineer
JD:Worked on DFT / MBIST / Scan cell insertionsWorked on more than million cell count projectworked on Soc DFT verification Good hold on timings and flops Good knowledge MBIST / CBIST/ Scan chain / Boundary scan insertions Good knowledge on Design for debug is added advantage
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DFT Engineer

SKANDYSYS PVT LTD

System Verilog Synthesis DFT Engineer DRC Cleaning
Hi,Greetings from SkandysysWe are currently hiring potential DFT Engineers, who are having 3+ years experience for our substantial ongoing and upcoming projects. Job location would be BangaloreGood practical exposure in the following list: Scan, Compression logic Insertion & DRC Cleaning MBIST Insertion & Verification The remuneration and perks are unmatchable in the market.Waiting for your positive outlook.
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