ASIC Verification Engineer Jobs

JD:Location:Bangalore/HyderabadExp:4+ Previously developed packet based test bench using UVM verification methodologyExperience in creating and maintaining block level test benches and converting them for top level usageExperience in random and directed test methods, coverage analysis (code coverage and functional coverage) and score boardingStrong System Verilog coding skillsUnderstanding of ASIC design and hands on RTL coding skillsExperience with high speed and network interfaces Expertise in Any one of the Protocols : Ethernet MAC and IP transport, PCIE, USB, DDR, MIPI, HDMI.SOC architectures, high speed interconnect buses such as AHB, APB and interfaces such as SERDES, I2C, Exposure to communications/DSP building blocks and/or SOC functional modulesRequired ExperienceStrong logical and creative problem-solving skills with excellent analytical and debugging skillsMust be a flexible self-starter who can ramp up with new technologies, products, etc.Motivated, and able to work effectively under pressureGood written and oral communication skills

Hello VLSI Professionals!!!We are hiring below positions:*Physical Design Engineer*Physical Verification Engineer*RTL Design Engineer*Design & verification Engineer*FPGA Design Engineer*DFT Engineer*Emulation Engineer*STA & SynthesisExperience Level : 3+ Years in relevance. (Freshers can also apply for Intern)Notice Period : Immediate-60 days.Work Location : Bangalore, Hyderabad and ChennaiSelected candidates will receive call letter for Technical roundsVLSI design has a promising future with several exciting trends and technologies emerging in the field. One of the key trends is the integration of System-on-Chip (SoC), which involves combining multiple functionalities onto a single chip. This integration enables higher performance, increased power efficiency, and reduced form factors for electronic devices.Another noteworthy trend is the continuous scaling down of transistor dimensions, which has been the driving force behind the historical growth of IC computing power. Shrinking transistor dimensions allows for increased transistor density and improved device performance. However, as transistor sizes approach their physical limits, alternative design and manufacturing techniques such as nanoscale technologies and 3D integration are being explored to further enhance the capabilities of VLSI systems.Additionally, VLSI design is closely tied with related fields such as artificial intelligence (AI) and Internet of Things (IoT). The growing demand for AI and IoT applications is pushing the development of VLSI systems that can support the processing and connectivity requirements of these technologies.

1. Brining up Linux environment on ARM2. Work will involve interfacing with a camera, display, and some image processing.3. Design implementation (FPGA design and simulation)4. Rapid prototyping, bring up and debug5. Comfortable in Linux environment.Note: Self-motivated, goal oriented and good analytical skills

IP verification Using SV/UVM SOC Verification using C/SV Third Party VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (3+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+) Memory Interfaces: DDR or HBM I/O (10+) Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incsive Technical Documentation: Testbench Specification, Test Plan Specification Foundry Porting Experience: Technology Library Conversion Related Changes Verification

Work Location: Bangalore / Hyderabad / Coimbatore. EXP- 5+Design Verification - Strong UVM/SV- IP and SOC DV- AXI- 5+ need to have strong protocol Exp such as DDR. PCIe, EthernetDesign Verification - Gate Level Simulations (GLS)- Gate Level Simulation (GLS) knowledge is must- IP and SOC DV- 5+ need to have strong GLS expRTL Design - NO FPGA engineers. They shall have worked on ASIC flow- Keywords - SPYGLASS, LEC, LINT, Synthesis,Emulation - UVM/SV- Synopsys Zebu- Transactor development OR running design with Firmware on ZebuFORMAL - Design Verification - Strong UVM/SV- Experience on Cadence Jasper Gold or Incisive formal verifier (IFV)- Connectivity Check, Register Validation etc.- 7+ need to have some protocol

Key Qualification 4+ years of experience with large FPGA development on Xilinx / Altera/ Microsemi Devices 4+ years of RTL development using Verilog / VHDL/ System-Verilog/UVM /C/C++ Well versed with FPGA design flow including design entry, synthesis, Implementation, place and route, timing constraints and timing closure In-depth background in HDL development, Verilog coding, integration, synthesis, debug, simulation, test bench creation Experienced with test planning, test bench architecture and assertions Constrained random verification experience with SystemVerilog and UVM Coverage driven verification (code/functional/assertion coverage) Demonstrated experience working on FPGA design projects, including work with SoC (ARM/RISC-V CPU), 10/ 40/ 100G Ethernet PHY, DDR#, PCI-E, SDIO interfaces. Hands on experience with lab debug equipment, such as oscilloscopes, logic analyzers, soldering Effectively communicate with cross functional team for bringing up designs Good knowledge with high speed bus protocols including AMBA/AXI3/AXI4 and low speed protocols including USB / SPI / UART/ IIC and other native protocols Experienced with ADC / DAC / EEPROM and other peripheral componentsPreferred Experience with SERDES / JESD204B /Gb PHY is PLUS Ability to communicate and work well with team Excellent interpersonal skills and self-motivation Ability to work well in a team and be productive under tight schedules Knowledge of computer architecture is plus Excellent written and verbal communication skills PCB-Schematic Reading Full Design Integration and debug Good understanding of low-level software and device drivers such as Firmware, Boot.

Required VLSI dsign engineers in DV, PD, DFT, Analog layout. Interested candidates send your resume