ASIC Verification Engineer Jobs

Xanbell Opening for Vlsi Design Engineer  ( 1 - 8 yrs)

RS 3,00,000 To 18,00,000 Hyderabad, Bangalore, Chennai, Noida

Dear Candidates, We have excellent opportunity for VLSI Design Engineers with below job description. Role Category: VLSI, Design , Electronics Education: B.Tech. /B.E , ME / M. Tech Experience : 1 - 8 Yrs Locations ...

Key Skills : vlsi,vlsi design,asic design

Low Power Physical Design Engineer  ( 4 yrs)

1. Expertise in Low PowerPhysical design and Static Timing Analysis Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verific...

Key Skills : physical design engineer,asic,physical design engineering,low power physical design

Design Verification Engineer  ( 3 - 9 yrs)

Design Verification • Very good system Verilog /UVM/OVM knowledge with prior work experience on live projects • Good logical thinking and excellent at solving the digital logic • Must have hands on experience in complete IP/SoC Verific...

Key Skills : uvm,syetemverilog,asic designing,design,design verification

Low Power Physical Design Engineers  ( 4 yrs)

1. Expertise in Low PowerPhysical design and Static Timing Analysis Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verific...

Key Skills : physical design engineer,physical design,low power physical design,asic,physical design engineering

Pcie – Logic Verification Engineer Us Captive R&d Center  ( 4 - 12 yrs)

RS 12,00,000 To 35,00,000 Bangalore

Role Responsibility Design, architect and implement testbench development and execution Involve in architectural decisions with design team during development phase Contribute in implementation of UVM based testbench and verif flow/autom...

Key Skills : asic verification engineer,pci,pcie,pcie gen 1,pcie gen 2,pcie gen 3,designing,verification engineering

Asic Verification Engineer  ( 4 - 15 yrs)

RS 7,00,000 To 20,00,000 Ahmedabad, Bangalore, Noida

Candidate Will Be Involved In Developing Testbench For The Block / Cluster, Testcases, Tesplans And Functional And Code Coverage Closure Activities And Reviews Of Documents And Code. Candidate Will Be Individually Responsible For Successful Delive...

Key Skills : asic verification engineer,senior asic verification engineer

ASIC Physical Design Engineer  ( 3 yrs)

 Bangalore

1. Should have worked on the entire PD Flow from netlist to GDS (Floorplanning, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI). 2. Should have very good idea about OCV/MM/MC and multi power designs (Level shifte...

Key Skills : physical design engineer,asic,asic engineer,asic design

Hiring Assistant Engineer VLSI Designs  ( 1 yrs)

VLSI Design Engineers has a training program for 6 - 9 months and work in Design, Modeling, Verification, FPGA Validation, and Product Validation for IPs, FPGAs, ASICs and SOCs as well as EDA Products working in areas of Verilog, SystemVerilog and V...

Key Skills : logic design,hdl,rtl,vhdl,verilog,system verilog,verification engineer,vlsi design engineer,vlsi engineer,vlsi designer

Walk-in for Asic Verification Engineers.  ( 2 - 10 yrs)

RS 1,50,000 To 5,00,000 Hyderabad

Work Location Hyderabad Experience 2 - 10 years Verification Engineer with 2-10 years of relevant experience in HVLs like SystemVerilog/SystemC and methodologies like UVM/OVM/VMM. Candidate should have excel...

Key Skills : asic engineer,pci,amba,axi,ahb,apb,uvm,ovm,vmm,hvl,system verilog,soc verification,asic verification engineering

Design Verification Engineers  ( 3 yrs)

RS 1,00,000 To 3,00,000 Bangalore

DV Engineers having experience in (System Verilog, UVM) Experience 3 Years to 8 Years Job Locations Bangalore, Shanghai, JD:- a ) SoC based verification: - Must have working knowledge of Verilog , System Verilog (HVL)

Key Skills : system verilog,uvm,ovm,axi,ace,ahb,apb,verilog,amba,data collection,data analyst,data...

Verification Engineer - Lead (pcie Expertise)  ( 5 - 10 yrs)

Job Description must have Very Good System Verilog/uvm Knowledge with Prior Work Experience On Live Projects expertise in Amba Bus Protocols and Arm Cpu experience in Developing Functional Verification Environments Including the Comp...

Key Skills : pcie,ethernet bus,system verilog,asic verification,perl,shell,scripting

Low Power Physical Design Engineer  ( 4 yrs)

Work experience in 45nm, 22nm, 14nm, or lower process technology - Good knowledge of digital design concepts - Good knowledge of ASIC design flow - Good team player and ability to work with stakeholders like RTL team, DFT team and verificati...

Key Skills : physical design engineer,physical design engineering,low power physical design

RTL Design and verification Engineer  ( 3 - 7 yrs)

RS 5,00,000 To 13,00,000 Bangalore

• Develop micro-architecture and RTL implementation. • Block level/ full chip integration and design. • Hands-on with Lint, CDC , LEC and preferably Low Power check tools • Some experience of AXI/AHB • design in System Verilog and timin...

Key Skills : asic synthesis,asic design,lint,cdc,synthesis,verilog,ovm,uvm,rtl,verification engineer,rtl design,system...

SOC level AMS verification Engineer / Lead / Manager  ( 4 - 10 yrs)

Requirements: • Analog and Mix signal block connectivity verification at RTL and gate level. • Integrate analog models with RTL and GATE simulation environment. • Define test strategy for Analog blocks - create test plan, define test concurr...

Key Skills : soc,gate,rtl,ams,ate,ams verification engineer,system verilog,asic design,vlsi design,circuit designing,analog...

Asic /SOC verification Engineer.  ( 5 - 7 yrs)

RS 3,00,000 To 12,00,000 Bangalore

Job Role: Asic /SOC verification Engineer. Experience: 5-7 Years Location: Bangalore Industry: Embedded Technology Job Description: In this role, a Senior Verification Consultant will be involved in verifying SoC and signal process...

Key Skills : soc,asic,uvm,verilog,test benches,cache coherent,set testing,embedded programmer,c programming,c++

Senior Verification Engineer  ( 2 - 7 yrs)

RS 5,00,000 To 12,00,000 Bangalore

1.Expertise in ASIC/SoC verification using HVLs. Knowledge of networking protocols will be an added advantage. 2.Expertise in SystemVerilog, Verification Methodologies such as OVM,UVM,etc. 3.Should have worked on at least one full-chip or module-le...

Key Skills : senior verification engineer,system verilog,ovm,uvm,verilog hdl,c,c++,soc,asic design,vlsi design,circuit...

ASIC Engineer  ( 8 yrs)

RS 15,00,000 To 20,00,000 Bangalore

- Experience : 8 - 12 Years - Location : Bangalore - 8+ Years of experience in ASIC Verification - Expert in System Verilog and verification methodologies - Expertise in Bus protocols - Experience with simulators, debug tools, and commercial v...

Key Skills : asic engineer,asic,asic design,uvm,system verilog,soc,vlsi design,circuit designing,analog circuit design,ic design

Senior Physical Design Engineer  ( 7 yrs)

RS 1,25,000 To 3,50,000 Bangalore

Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. - Participating in establishing physical design methodologies, flow automation, chip floor pla...

Key Skills : physical design engineers,vlsi design engineer,vlsi-very large scale integration,senior cad designer,vlsi design...

Requirement of Lead Engineer (memory Circuit Design)  ( 8 yrs)

RS 1,25,000 To 3,50,000 Bangalore, Noida

Job Responsibility Involves Full Ownership of Complete Memory Development Process Starting from Freezing of Specifications , Forming the Verification Plan , Ensuring the Timely Approvals from Customer , Self Execution of Memory Design , Verification.

Key Skills : design verification,circuit designing,memory designing,memory circuit designing,lead engineer,civil lead engineer,lead generation...

Engineer - IC Design  ( 6 yrs)

RS 1,25,000 To 3,50,000 Bangalore

The Position Requires An Energetic, Proactive, Self-starting Person, Who is Able to Lead and Coordinate Full Chip DFT Task and Work Closely with other DFT Engineers to Explore New Methodologies. You Must Possess Strong Technical Knowledge in the Area...

Key Skills : design engineer,electrical engineering,rf,asic designing,power distribution,electrical technician,electrical maintenance