job details :- job description: positions are open for full-time and co-op/internship in the areas of soc physical implementation from unit level to chip level, involving all aspects of physical design functions such as p&r, timing,floorplan,clocking,electrical analysis, and power. responsibilities - own block level design from rtl-to-gdsll and drive synthesis, floor-planning,place & route,timing closure, and signoff. - work extensively with micro-architects to perform feasibility studies and explore performance, power & area (ppa) tradeoffs for design closure. - develop physical design methodologies and customize recipes across various implementation steps to optimize ppa. - work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as timing, power,em/ir, pdv. requirements - knowledge using synthesis, place & route,analysis and verification cad tools. - familiarity with logic & physical design principles to drive low-power & higher-performance designs. • knowledge of scripting in some of these languages: unix, perl,python,and tcl. - good understanding of device physics and experience in deep sub-micron technologiesknowledge of verilog and systemverilog. - excellent skills in problem solving, written and verbal communication,excellent organization skills, and highly self-motivated. - ability to work well in a team and be productive under aggressive schedules. education and experience - phd, master's degree or bachelor's degree in technical subject area. hiring candidates who have experience in semiconductors which have a study background in electrical or electronics. dm for contact information.
Experience
5 - 11 Years
No. of Openings
40
Education
B.E, M.Tech, Ph.D/Doctorate
Role
Electrical Analyst
Industry Type
Engineering / Cement / Metals
Gender
[ Male / Female ]
Job Country
India
Type of Job
Full Time
Work Location Type
Work from Home