VLSI-Very Large Scale Integration Jobs

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Hello VLSI Professionals!!!We are hiring below positions:*Physical Design Engineer*Physical Verification Engineer*RTL Design Engineer*Design & verification Engineer*FPGA Design Engineer*DFT Engineer*Emulation Engineer*STA & SynthesisExperience Level : 3+ Years in relevance. (Freshers can also apply for Intern)Notice Period : Immediate-60 days.Work Location : Bangalore, Hyderabad and Chennai**Selected candidates will receive call letter for Technical rounds**VLSI design has a promising future with several exciting trends and technologies emerging in the field. One of the key trends is the integration of System-on-Chip (SoC), which involves combining multiple functionalities onto a single chip. This integration enables higher performance, increased power efficiency, and reduced form factors for electronic devices.Another noteworthy trend is the continuous scaling down of transistor dimensions, which has been the driving force behind the historical growth of IC computing power. Shrinking transistor dimensions allows for increased transistor density and improved device performance. However, as transistor sizes approach their physical limits, alternative design and manufacturing techniques such as nanoscale technologies and 3D integration are being explored to further enhance the capabilities of VLSI systems.Additionally, VLSI design is closely tied with related fields such as artificial intelligence (AI) and Internet of Things (IoT). The growing demand for AI and IoT applications is pushing the development of VLSI systems that can support the processing and connectivity requirements of these technologies.

Job DescriptionResponsibilities:Preparation of digital design test plan from requirements using Cadence-vManager / vPlannerDefinition and creation of UVM-SV test environment, test plans, tests, and functional coverageVerification of signal processing and control algorithms using Cadence and MathWorks toolsAnalysis of test results, improving test coverage, and debug of unexpected design behaviorRunning and maintenance of regression runs0p-Preparation and/or leading of verification reviewsModification and/or debug of Simulink models in mixed signal test environmentCoordination of verification activities with abroad team membersCooperation with system engineering team on Jama requirementsMandatory skills:Possess at least a BSEE (MSEE preferred)Should have 6-8yrsl years' experience in digital design and/or digital verificationMust be knowledgeable in digital design fundamentalsKnowledge of Universal Verification Methodology, System Verilog assertions, and Cadence verification tools is a mustExperience with the usage of Jama requirements management, MATLAB/Simulink model, and Python programming is a strong plusSkills, Knowledge, and AptitudesExcellent communication, documentation, problem-solving and analytical skills are requiredAble to solve challenging problems during verification and debugAbility to supervise and mentor junior engineers

Job DescriptionResponsibilities:Preparation of digital design test plan from requirements using Cadence-vManager / vPlannerDefinition and creation of UVM-SV test environment, test plans, tests, and functional coverageVerification of signal processing and control algorithms using Cadence and MathWorks toolsAnalysis of test results, improving test coverage, and debug of unexpected design behaviorRunning and maintenance of regression runs0p-Preparation and/or leading of verification reviewsModification and/or debug of Simulink models in mixed signal test environmentCoordination of verification activities with abroad team membersCooperation with system engineering team on Jama requirementsMandatory skills:Possess at least a BSEE (MSEE preferred)Should have 6-8yrsl years' experience in digital design and/or digital verificationMust be knowledgeable in digital design fundamentalsKnowledge of Universal Verification Methodology, System Verilog assertions, and Cadence verification tools is a mustExperience with the usage of Jama requirements management, MATLAB/Simulink model, and Python programming is a strong plus

Work Location: Bangalore / Hyderabad / Coimbatore. EXP- 5+Design Verification - Strong UVM/SV- IP and SOC DV- AXI- 5+ need to have strong protocol Exp such as DDR. PCIe, EthernetDesign Verification - Gate Level Simulations (GLS)- Gate Level Simulation (GLS) knowledge is must- IP and SOC DV- 5+ need to have strong GLS expRTL Design - NO FPGA engineers. They shall have worked on ASIC flow- Keywords - SPYGLASS, LEC, LINT, Synthesis,Emulation - UVM/SV- Synopsys Zebu- Transactor development OR running design with Firmware on ZebuFORMAL - Design Verification - Strong UVM/SV- Experience on Cadence Jasper Gold or Incisive formal verifier (IFV)- Connectivity Check, Register Validation etc.- 7+ need to have some protocol

JD:Location:Bangalore/HyderabadExp:4+ Previously developed packet based test bench using UVM verification methodologyExperience in creating and maintaining block level test benches and converting them for top level usageExperience in random and directed test methods, coverage analysis (code coverage and functional coverage) and score boardingStrong System Verilog coding skillsUnderstanding of ASIC design and hands on RTL coding skillsExperience with high speed and network interfaces Expertise in Any one of the Protocols : Ethernet MAC and IP transport, PCIE, USB, DDR, MIPI, HDMI.SOC architectures, high speed interconnect buses such as AHB, APB and interfaces such as SERDES, I2C, Exposure to communications/DSP building blocks and/or SOC functional modulesRequired ExperienceStrong logical and creative problem-solving skills with excellent analytical and debugging skillsMust be a flexible self-starter who can ramp up with new technologies, products, etc.Motivated, and able to work effectively under pressureGood written and oral communication skills

Hiring Now!VLSI EngineerAnalog layoutExperience 4+yearsLocation: Bangalore

Job Description- Candidate should have good exposure of analog layout concepts like matching, shielding etc.- The selected candidate will work on floorplan, Layout and verification(DRC/LVS) of various analog and mixed signal blocks like amplifiers, references, regulators (LDO/DCDC Buck, Boost, Multiphase), PLL, ADC, DAC across a wide range of technologies from scratch.- Will have to interact with design teams to ensure on time meeting all the design requirement.- Must be technically independent, and able to work in a multi-site team environment.- Strong verbal & written communication skills are desired

Required VLSI dsign engineers in DV, PD, DFT, Analog layout. Interested candidates send your resume