Verification Engineer 10th Pass Experience Jobs in Bangalore

Senior Power Aware Verification Engineer - Job Description**Company:** **Department:** VLSI Design & Verification**Industry:** Semiconductors / Embedded Systems**Location:** Bangalore, India**Experience:** 7+ YearsJob OverviewWe are seeking a highly skilled Senior Power Aware Verification Engineer with expertise in low-power design methodologies and processor-based verification environments. The ideal candidate should have strong hands-on experience in UPF (Unified Power Format) and a deep understanding of low power architecture, along with a proven track record in processor-based verification workflows.Key Responsibilities- Perform power-aware verification for complex SoC designs.- Develop, execute, and maintain verification test plans for low-power architecture.- Work with UPF to model and verify power domains, power states, and transitions.- Collaborate with design and architecture teams to ensure compliance with low-power design intent.- Debug and resolve power-aware simulation issues.- Create verification environments for processor-based architectures.- Mentor junior engineers in low-power verification methodologies.Required Skills & Qualifications- 7+ years of hands-on experience in Power Aware Verification.- Strong knowledge of UPF and low-power design verification techniques.- Experience with processor-based verification environments.- Solid understanding of digital design fundamentals and SoC architectures.- Proficiency in SystemVerilog/UVM or equivalent verification methodologies.- Strong problem-solving and debugging skills.- Excellent communication and teamwork abilities.Preferred Skills- Experience in scripting languages (Perl, Python, Tcl).- Familiarity with EDA tools from Synopsys, Cadence, or Mentor Graphics for power-aware simulation.Employment TypeFull-Time, Permanent

Job DescriptionResponsibilities:Preparation of digital design test plan from requirements using Cadence-vManager / vPlannerDefinition and creation of UVM-SV test environment, test plans, tests, and functional coverageVerification of signal processing and control algorithms using Cadence and MathWorks toolsAnalysis of test results, improving test coverage, and debug of unexpected design behaviorRunning and maintenance of regression runs0p-Preparation and/or leading of verification reviewsModification and/or debug of Simulink models in mixed signal test environmentCoordination of verification activities with abroad team membersCooperation with system engineering team on Jama requirementsMandatory skills:Possess at least a BSEE (MSEE preferred)Should have 6-8yrsl years' experience in digital design and/or digital verificationMust be knowledgeable in digital design fundamentalsKnowledge of Universal Verification Methodology, System Verilog assertions, and Cadence verification tools is a mustExperience with the usage of Jama requirements management, MATLAB/Simulink model, and Python programming is a strong plus