senior power aware verification engineer - job description
**company:**
**department:** vlsi design & verification
**industry:** semiconductors / embedded systems
**location:** bangalore, india
**experience:** 7+ years
job overview
we are seeking a highly skilled senior power aware verification engineer with expertise in low-power design methodologies and processor-based verification environments. the ideal candidate should have strong hands-on experience in upf (unified power format) and a deep understanding of low power architecture, along with a proven track record in processor-based verification workflows.
key responsibilities
- perform power-aware verification for complex soc designs.
- develop, execute, and maintain verification test plans for low-power architecture.
- work with upf to model and verify power domains, power states, and transitions.
- collaborate with design and architecture teams to ensure compliance with low-power design intent.
- debug and resolve power-aware simulation issues.
- create verification environments for processor-based architectures.
- mentor junior engineers in low-power verification methodologies.
required skills & qualifications
- 7+ years of hands-on experience in power aware verification.
- strong knowledge of upf and low-power design verification techniques.
- experience with processor-based verification environments.
- solid understanding of digital design fundamentals and soc architectures.
- proficiency in systemverilog/uvm or equivalent verification methodologies.
- strong problem-solving and debugging skills.
- excellent communication and teamwork abilities.
preferred skills
- experience in scripting languages (perl, python, tcl).
- familiarity with eda tools from synopsys, cadence, or mentor graphics for power-aware simulation.
employment type
full-time, permanent