Senior Power Aware Verification Engineer - Job Description
**Company:**
**Department:** VLSI Design & Verification
**Industry:** Semiconductors / Embedded Systems
**Location:** Bangalore, India
**Experience:** 7+ Years
Job Overview
We are seeking a highly skilled Senior Power Aware Verification Engineer with expertise in low-power design methodologies and processor-based verification environments. The ideal candidate should have strong hands-on experience in UPF (Unified Power Format) and a deep understanding of low power architecture, along with a proven track record in processor-based verification workflows.
Key Responsibilities
- Perform power-aware verification for complex SoC designs.
- Develop, execute, and maintain verification test plans for low-power architecture.
- Work with UPF to model and verify power domains, power states, and transitions.
- Collaborate with design and architecture teams to ensure compliance with low-power design intent.
- Debug and resolve power-aware simulation issues.
- Create verification environments for processor-based architectures.
- Mentor junior engineers in low-power verification methodologies.
Required Skills & Qualifications
- 7+ years of hands-on experience in Power Aware Verification.
- Strong knowledge of UPF and low-power design verification techniques.
- Experience with processor-based verification environments.
- Solid understanding of digital design fundamentals and SoC architectures.
- Proficiency in SystemVerilog/UVM or equivalent verification methodologies.
- Strong problem-solving and debugging skills.
- Excellent communication and teamwork abilities.
Preferred Skills
- Experience in scripting languages (Perl, Python, Tcl).
- Familiarity with EDA tools from Synopsys, Cadence, or Mentor Graphics for power-aware simulation.
Employment Type
Full-Time, Permanent