Principal Design Engineer Jobs

Responsibilities:Lead end-to-end verification from complex CPU sub-units up to CPU clusters, partnering with architecture and design teamsDevelop verification infrastructure components including test-benches, scoreboards, and stimulus generatorsDevelop and execute comprehensive verification plans for units and featuresImplement functional coverage modelsDebug designs in simulation, prototyping platforms, and siliconContinuously drive methodology improvements to improve efficiencyLead senior and junior engineers as a team to accomplish successful projectsMinimum Qualifications: Bachelors or Masters degree in electrical, computer engineering or related fieldBS+10 years or MS+12 years of industry experience successfully delivering CPU implementationsSkills & Qualifications Required: System Verilog verification development experienceTest bench construction using UVM or analogous methodologiesScoreboards and stimulus generators for complex unitsStrong background in one or more common CPU ISAs. x86, ARM, MIPS, RISC-V, etc.Strong background in processor coherency and MP programmingProject ownership throughout the project lifecycle Demonstrated team leadership experience with outstanding communication skills Highly motivated self-starter with strong execution mindset and collaborative approachPost-silicon debug experience strongly preferred

Role: Principal EngineerLocation: BangaloreDuration: 12 months.Mode of Work: HybridRequired Services and qualifications:Services:1. Design and implement next-generation networking technologies.2. Deploy/support large-scale production network.3. Track, analyze, and trend capacity on the broadcast network and datacentreinfrastructure.4. Provide Tier 3 escalated network support.5. Perform fault management and problem resolution.6. Work closely with other departments, vendors, and service providers.7. Perform network change management, support modifications, and maintenance.8. Perform network upgrade, maintenance, and repair work.9. Lead implementation of new systems.10. Perform capacity planning and management.11. Suggest opportunities for improvement.12. Create and support network management objectives, policies, and procedures.13. Ensure network documentation is kept up to date; and14. Train and assist junior engineers.Required Qualifications and Certifications:1. Routing - Switching, Load Balancers (GTM, RTM), Firewalls2. Cisco ACI - Design and Implementation3. Routing Protocols (BGP, EIGRP & OSPF), VRFs, VLANs, VRRP,LACP, MLAG, IP Multicast, VPC, Transit Gateway, NAT / SNAT4. Security Groups, ACL, HSRP, VRRP, SNMP, DHCP5. AWS (VPC, API Gateway, CloudFront, Route 53, Cloud WAN, DirectConnect, Private Link, Transit Gateway)6. CCIE, AWS Certified Advanced NetworkingPreferred Qualifications:1. Elastic Load Balancing (ELB), DNS / DHCP, IPSec VPN, Multicast, TACACS/ Rancid / GIT, ALB/ELB2. AWS Control Tower

About Company :SiMa is a machine learning company transforming the embedded edge market through high-performance compute at the lowest power. Initially focused on computer vision applications, the company's software-first approach simplifies ML integration and supports the broadest set of capabilities through a purpose-built MLSoC platform, enabling rapid adoption and creating the best of ease-of-use experience. SiMa.ai is led by technologists and business veterans and backed by a set of top investors committed to helping customers scale machine learning at the edge. For more informationJob Description :- As the Hardware Design Verification Engineer, you will help lead and develop the verification methodology for SiMa.ai's MLSoC- .- As the Lead, you will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support.- You will work very closely with the Architecture, RTL/uArch, and cross-functional teams.Areas of focus :Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team.Minimum Qualifications :- BS in Computer Science/EE with 15+ years of experience or MS in Computer Science/EE with 12+ years of experience in HW Design Verification.- Experience with block level, cluster level or chip/SoC level verification.- Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, System Verilog.- Expertise in scripting languages, python or perl.- Strong experience in helping emulation and validation.- Experience with modeling various HW blocks, IPs for verification, emulation.- Ability to analyze systems-level performance, profiling, and analysis.