Senior ASIC FPGA Design & Verification Engineer ( 2 - 8 yrs)
ATRIA LOGIC PRIVATE LIMITED
RS 4,00,000 To 10,00,000 p.a. Bangalore
• As a Design engineer should be able to develop design specs, HDL based RTL • Strong knowledge on Digital design concepts with RTL implementation (Verilog/VHDL) • Experience with FPGA/ASIC tool flows for Logic Synthesis, STA and Frontend...
Key Skills : Verification Engineer,Design Engineer
FPGA Design Engineer fresher ( 0 - 6 yrs)
RS 2,00,000 To 6,00,000 p.a. Bangalore
This is to inform you that we are looking for FPGA design Engineers for our development project. The candidates shall have Good HDL programming skill with good knowledge in FPGA flow and its development tools. The candidate should hav...
Key Skills : FPGA,VHLD,Verilog,Xilinx ISE,ModelSim