DFT Engineer Jobs

We are seeking experienced DFT Engineers with expertise in Scan, ATPG, and MBIST for SoC / ASIC designs. This role focuses on implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness. Key ResponsibilitiesImplement and verify Scan, ATPG, and MBIST for complex SoCs.Perform pattern generation, coverage analysis, and debug.Integrate and validate MBIST with memory test algorithms.Collaborate with RTL and Physical Design teams for smooth DFT integration and sign-off.Develop automation scripts to streamline DFT flows. Required Skills4 to 10 years of DFT experience in ASIC / SoC environments. (Rs 22L to Rs 28L per annum)Hands-on expertise with EDA tools:Synopsys (DFT Compiler, TestMAX, TetraMAX)Cadence ModusPreferred: Siemens Tessent / FastScanStrong understanding of fault models (stuck-at, transition, path delay).Knowledge of MBIST architecture and memory test techniques.Scripting skills in TCL, Perl, Python.Familiarity with RTL design flows, STA constraints, and silicon bring-up.Send your resumes to mstechtalentacq@gmail.com and we will contact you.

Good knowledge of all the DFT concepts & ATPG Flows. Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements. Stuck-At, Transition Delay fault models test pattern generations and Simulations. Expertise in Scan Compression, BSCAN /JTAG and MBIST implementation and verification. Good problem solving and debugging skills. Proactive in nature. Experience in writing scripts in perl/tcl for automation. Sound hands on Experience with industry standard DFT tools & flows(Mentor, Synopsys or Cadence ) Familiarity with Timing constrains development, LEC & Post Silicon ATE Bring-up will be added advantage

JD:Worked on DFT / MBIST / Scan cell insertionsWorked on more than million cell count projectworked on Soc DFT verification Good hold on timings and flops Good knowledge MBIST / CBIST/ Scan chain / Boundary scan insertions Good knowledge on Design for debug is added advantage

Hello VLSI Professionals!!!We are hiring below positions:*Physical Design Engineer*Physical Verification Engineer*RTL Design Engineer*Design & verification Engineer*FPGA Design Engineer*DFT Engineer*Emulation Engineer*STA & SynthesisExperience Level : 3+ Years in relevance. (Freshers can also apply for Intern)Notice Period : Immediate-60 days.Work Location : Bangalore, Hyderabad and ChennaiSelected candidates will receive call letter for Technical roundsVLSI design has a promising future with several exciting trends and technologies emerging in the field. One of the key trends is the integration of System-on-Chip (SoC), which involves combining multiple functionalities onto a single chip. This integration enables higher performance, increased power efficiency, and reduced form factors for electronic devices.Another noteworthy trend is the continuous scaling down of transistor dimensions, which has been the driving force behind the historical growth of IC computing power. Shrinking transistor dimensions allows for increased transistor density and improved device performance. However, as transistor sizes approach their physical limits, alternative design and manufacturing techniques such as nanoscale technologies and 3D integration are being explored to further enhance the capabilities of VLSI systems.Additionally, VLSI design is closely tied with related fields such as artificial intelligence (AI) and Internet of Things (IoT). The growing demand for AI and IoT applications is pushing the development of VLSI systems that can support the processing and connectivity requirements of these technologies.