Good knowledge of all the DFT concepts & ATPG Flows. Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements. Stuck-At, Transition Delay fault models test pattern generations and Simulations. Expertise in Scan Compression, BSCAN /JTAG and MBIST implementation and verification. Good problem solving and debugging skills. Proactive in nature. Experience in writing scripts in perl/tcl for automation. Sound hands on Experience with industry standard DFT tools & flows(Mentor, Synopsys or Cadence ) Familiarity with Timing constrains development, LEC & Post Silicon ATE Bring-up will be added advantage