RS 50,000 To 15,00,000 Hyderabad, Bangalore
Design Verification • Very good system Verilog /UVM/OVM knowledge with prior work experience on live projects • Good logical thinking and excellent at solving the digital logic • Must have hands on experience in complete IP/SoC Verific...
Key Skills : UVM,Syetemverilog,ASIC Designing
RS 1,25,000 To 3,50,000 Bangalore
The Position Requires An Energetic, Proactive, Self-starting Person, Who is Able to Lead and Coordinate Full Chip DFT Task and Work Closely with other DFT Engineers to Explore New Methodologies. You Must Possess Strong Technical Knowledge in the Area...
Key Skills : Design Engineer,Electrical Engineering,RF,ASIC designing