• Very good system Verilog /UVM/OVM knowledge with prior work experience on live projects
• Good logical thinking and excellent at solving the digital logic
• Must have hands on experience in complete IP/SoC Verific...
- Expertise in Low PowerPhysical design and Static Timing Analysis
- Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verifi...
1.Expertise in ASIC/SoC verification using HVLs. Knowledge of networking protocols will be an added advantage.
2.Expertise in SystemVerilog, Verification Methodologies such as OVM,UVM,etc.
3.Should have worked on at least one full-chip or module-le...
Exp. of Network Based Project, Protocol Development Programming is Must
desired Technical Skills (must Have):
- Experience in Design & Implementation of Layer2/3/4 Networking Features in Embedded Ip Routers and Switches (or Sdk for a Netwo...
The Position Requires An Energetic, Proactive, Self-starting Person, Who is Able to Lead and Coordinate Full Chip DFT Task and Work Closely with other DFT Engineers to Explore New Methodologies. You Must Possess Strong Technical Knowledge in the Area...
- Engineer Will Be Responsible for Designing the Asic to Meet the Specifications Defined.
- Responsible for Defining and Implementing Micro-architecture Design and Development of Various Functional Blocks.
- Responsible for Design of Soc-level Log...
Key Skills : soc design,asic design,rtl design,dft system verilog,digital designer,digital artist
• Develop micro-architecture and RTL implementation.
• Block level/ full chip integration and design.
• Hands-on with Lint, CDC , LEC and preferably Low Power check tools
• Some experience of AXI/AHB
• design in System Verilog and timin...
This is Vaibhav from SSJ Solutions and we have some exciting career options for you.
We have been providing exciting career options at senior/middle levels (from CEOs, SBU Heads down to PMs/PLs) since 1991 in IT/Software, Telecom, Finance, HRD for I...
- Expertise in Low PowerPhysical design and Static Timing Analysis.
- Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Ver...
Job Responsibility Involves Full Ownership of Complete Memory Development Process Starting from Freezing of Specifications , Forming the Verification Plan , Ensuring the Timely Approvals from Customer , Self Execution of Memory Design , Verification.
Expertise in Low PowerPhysical design and Static Timing Analysis
Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verificat...
We have an urgent requirement for the below position for a Steel Structural Engineering company in Chennai
Structual Steel Tekla‘Modeler and detailer ’ – Mid & Senior Grades
Should work in autocad and Tekla
Min.yrs – 2 to 3 yrs Experienc...
RS 90,000 To 1,25,000 Haridwar, Kashipur, Rudrapur-Udham, Sitarganj
Hiring for urgent opening for Electronics and Electrical Engineers.
Skills Required: Production, Quality, maintenance, PLC, e-CAD, SCADA, VLSI Design,
Candidate should be flexible to work in different domains.
Functional Area: Production, Manu...
Clipocruit Job Placements & Career Counseeling Pvt Ltd
RS 6,00,000 To 16,00,000 Hyderabad
• Analog and Mix signal block connectivity verification at RTL and gate level.
• Integrate analog models with RTL and GATE simulation environment.
• Define test strategy for Analog blocks - create test plan, define test concurr...
DV Engineers having experience in (System Verilog, UVM)
Experience 3 Years to 8 Years
Job Locations Bangalore, Shanghai,
a ) SoC based verification:
- Must have working knowledge of Verilog , System Verilog (HVL)
Key Skills : system verilog,uvm,ovm,axi,ace,ahb,apb,verilog,amba,data collection,data analyst,data...
-The selected intern candidate will be part of the IP verification/ VIP team in Group, smartchip design , India and be based at Bangalore.
-The focus area of activities would be Verification/ VIP/ Test Environment devel...
- Experience : 8 - 12 Years
- Location : Bangalore
- 8+ Years of experience in ASIC Verification
- Expert in System Verilog and verification methodologies
- Expertise in Bus protocols
- Experience with simulators, debug tools, and commercial v...
RS 1,75,000 To 4,50,000 North Delhi, South Delhi, East Delhi, West Delhi
As An Application Engineer You Will Work Directly, Sometimes in Great Depth, with Customers to Understand Their Technical and Business Challenges and Help Them Appreciate How to Apply Our Products Toward the Resolution of Their Problems.
Understanding of Bluetooth feature
Understanding of Core specification and at least 2 classic profiles
Understanding of LE core specification Desirable
Strong C work experience, C++ knowledge desirable
Key Skills : bluetooth developer,bluetooth development,chip designing