ASIC Physical Design Engineer ( 3 yrs)
Bangalore
1. Should have worked on the entire PD Flow from netlist to GDS (Floorplanning, Power Planning, Placement & Optimization, CTS, Routing, ECO steps, Timing/SI). 2. Should have very good idea about OCV/MM/MC and multi power designs (Level shifte...
Key Skills : Physical Design Engineer
RS 15,00,000 To 20,00,000 Bangalore
- Experience : 8 - 12 Years - Location : Bangalore - 8+ Years of experience in ASIC Verification - Expert in System Verilog and verification methodologies - Expertise in Bus protocols - Experience with simulators, debug tools, and commercial v...
Key Skills : ASIC Engineer,ASIC,ASIC Design,uvm
Embedded VLSI ASIC Chip Design Engineer at Bangalore ( 2 - 5 yrs)
Posted on 82 days ago
Guru Jobs India
RS 5,00,000 To 20,00,000 Bangalore
Layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc. Should have worked on 16nm and below technology nodes on various analog mixed signal blocks such as PLL, Band gap, ADC, DAC, SERDES, IO etc. Engineer sh...
Key Skills : VLSI Design Engineer,ASIC Designing,Chip Design
Looking for Physical Design Engineer ( 4 yrs)
RS 5,00,000 To 10,00,000 Bangalore
- Expertise in Low PowerPhysical design and Static Timing Analysis - Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verifi...
Key Skills : ,ASIC Design
Required Digital Design Engineer ( 4 yrs)
RS 1,00,000 To 3,00,000 Hyderabad, Secunderabad
- Engineer Will Be Responsible for Designing the Asic to Meet the Specifications Defined. - Responsible for Defining and Implementing Micro-architecture Design and Development of Various Functional Blocks. - Responsible for Design of Soc-level Log...
Key Skills : SOC Design,ASIC Design,RTL Design,DFT System Verilog
Required Senior Engineer Expertise in Low Power Physical Design ( 4 yrs)
RS 5,00,000 To 10,00,000 Bangalore
Expertise in Low PowerPhysical design and Static Timing Analysis Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verificat...
Key Skills : Senior Engineer,Low Power Physical design,ASIC Design
RS 1,25,000 To 3,50,000 Bangalore
The Position Requires An Energetic, Proactive, Self-starting Person, Who is Able to Lead and Coordinate Full Chip DFT Task and Work Closely with other DFT Engineers to Explore New Methodologies. You Must Possess Strong Technical Knowledge in the Area...
Key Skills : Design Engineer,Electrical Engineering,RF,ASIC designing
Hiring for Physical Design Engineer ( 4 yrs)
RS 5,00,000 To 10,00,000 Bangalore
- Expertise in Low PowerPhysical design and Static Timing Analysis. - Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Ver...
Key Skills : Physical Design Engineers,Low Power Physical design,Static Timing Analysis,digital design,ASIC
Design Verification Engineer ( 3 - 9 yrs)
RS 50,000 To 15,00,000 Hyderabad, Bangalore
Design Verification • Very good system Verilog /UVM/OVM knowledge with prior work experience on live projects • Good logical thinking and excellent at solving the digital logic • Must have hands on experience in complete IP/SoC Verific...
Key Skills : UVM,Syetemverilog,ASIC Designing
RTL Design and verification Engineer ( 3 - 7 yrs)
RS 5,00,000 To 13,00,000 Bangalore
• Develop micro-architecture and RTL implementation. • Block level/ full chip integration and design. • Hands-on with Lint, CDC , LEC and preferably Low Power check tools • Some experience of AXI/AHB • design in System Verilog and timin...
Key Skills : ASIC Synthesis,ASIC Design,lint,cdc,Synthesis,Verilog,ovm,uvm,RTL,Verification Engineer,RTL design
Seeking for VLSI Design Engineer ( 0 - 1 yrs)
RS 50000 To 60,000 Bangalore
Internship Descriptions: -The selected intern candidate will be part of the IP verification/ VIP team in Group, smartchip design , India and be based at Bangalore. -The focus area of activities would be Verification/ VIP/ Test Environment devel...
Key Skills : VLSI Design Engineer,VLSI Design,Verification Engineer,ASIC Engineer,ASIC,Verilog
Low Power Physical Design Engineer ( 4 yrs)
RS 5,50,000 To 10,00,000 Bangalore
1. Expertise in Low PowerPhysical design and Static Timing Analysis Experience in Netlist-GDS flow which includes Synthesis, Layout(Floorplan, Place and Route, CTS (clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verific...
Key Skills : Physical Design Engineer,ASIC
RS 1,75,000 To 4,50,000 North Delhi, South Delhi, East Delhi, West Delhi
As An Application Engineer You Will Work Directly, Sometimes in Great Depth, with Customers to Understand Their Technical and Business Challenges and Help Them Appreciate How to Apply Our Products Toward the Resolution of Their Problems.
Key Skills : Application Engineer,SimuLink,ASIC Design,application engineering
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