Posted on 89 days ago
RS 10,00,000 To 30,00,000 p.a. Ahmedabad
Minimum 2 years of experience in System Verilog HVL SVA Assertions. Must have executed at-least 2 SoC/IP Formal Verification signoff projects. Must have used Synopsys VC Formal , Cadence Jasper or Questa Formal Tools comprehensively ...
Key Skills : HVL,SVA,SV,Design Verification Engineer,Design Engineer,
Global Talent Pool
RS 6,00,000 To 15,00,000 p.a. Bangalore
knowledge with prior work experience on live projects. Expertise in creating detailed test plan with well-defined functional coverage. • Should be able to architect and implement self generating / self checking simulation verificati...
Key Skills : uvm,sv,design verification engineer,design engineer
RS 1,50,000 To 4,25,000 p.a. Bangalore, Kochi, Pune, Noida
• You will be part of the team verifying IPs and SoCs leading to first Si success. • IP verification is coverage driven using latest industry standard methodologies and HVLs. • Work involves defining verification strategy, writing test pl...
Key Skills : Design Engineer,C,C++
Shree Adishakthi Consultancy
RS 5,00,000 To 20,00,000 p.a. Bangalore
Layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc. Should have worked on 16nm and below technology nodes on various analog mixed signal blocks such as PLL, Band gap, ADC, DAC, SERDES, IO etc. Engineer sh...
Key Skills : VLSI Design Engineer,ASIC Designing,Chip Design