Techsquare

Vidyaranyapura, Bangalore

Requirements often include:Strong proficiency in Verilog/VHDL or SystemVerilog.Knowledge of digital design principles.Understanding of ASIC design flows.Experience with synthesis, place and route tools.Knowledge of FPGA architectures.Experience with FPGA design tools.Understanding of timing analysis and optimization.Knowledge of verification methodologies (e.g., UVM).Experience with simulation tools.Ability to write test benches and develop test plansTools:Synthesis Tools:Synopsys Design Compiler: A widely used synthesis tool.Cadence Genus Synthesis Solution: Another industry-standard tool.Xilinx Vivado: Includes synthesis tools for Xilinx FPGAs.Intel Quartus Prime: Includes synthesis tools for Intel FPGAs.Simulators:Verilator:Icarus Verilog: A free and open-source Verilog simulation and synthesis tool.For any further query kindly contact: Hemath Kumar :-8496929937.Job Types: Full-time, InternshipContract length: 21 monthsPay: 160,000.00 - 430,000.00 per yearBenefits:Health insuranceProvident FundSchedule:Day shiftSupplemental Pay:Performance bonusWork Location: In personApplication Deadline: 15/03/2025