Concordit Systems

Hyderabad, Telangana

Job DescriptionResponsibilities:Preparation of digital design test plan from requirements using Cadence-vManager / vPlannerDefinition and creation of UVM-SV test environment, test plans, tests, and functional coverageVerification of signal processing and control algorithms using Cadence and MathWorks toolsAnalysis of test results, improving test coverage, and debug of unexpected design behaviorRunning and maintenance of regression runs0p-Preparation and/or leading of verification reviewsModification and/or debug of Simulink models in mixed signal test environmentCoordination of verification activities with abroad team membersCooperation with system engineering team on Jama requirementsMandatory skills:Possess at least a BSEE (MSEE preferred)Should have 6-8yrsl years' experience in digital design and/or digital verificationMust be knowledgeable in digital design fundamentalsKnowledge of Universal Verification Methodology, System Verilog assertions, and Cadence verification tools is a mustExperience with the usage of Jama requirements management, MATLAB/Simulink model, and Python programming is a strong plusSkills, Knowledge, and AptitudesExcellent communication, documentation, problem-solving and analytical skills are requiredAble to solve challenging problems during verification and debugAbility to supervise and mentor junior engineers