Concord IT Systems

Hyderabad, Telangana

Role:- AMS Verification Engineer / LeadJobLocation: Hyd/BLRExperience: 7+ yearsSkills: AMS & wreal modeling, SV modeling and Testbench development, spectre/spice simulations, Basics of UVM, python and perl scriptingRoles and Responsibilities BE/B.Tech in ECE /M.Tech in VLSI with 7 years experience in Analog Mixed Signal Verification Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks Very Good experience in Analog Mixed Signal verification simulation tools Good experience in System Verilog, UVM methodologies Able to train the team members and guide them to the solutions for problems Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch. Good experience in Gate level netlist simulation Experience in Python, Perl, Shell scripting is added advantage. Good communication and documentation skills

Role:-physical designLocation: Hyderabad/BangaloreJob Description SummaryWill be working closely with Physical design teams for Managing deliverables.Customer interactions, execution and planning. Mentor the team technically and ensure efficient project management.Under general direction is responsible for performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging ofJob Description: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes. Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2) Strong experience on Static Timing Analysis (PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre). Understanding the practical application of methodologies and Physical Design Tools, Flow Automation, and Improvements. Experience in complex SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techniques.Leading junior teams, Training and Mentoring. Project Management.Excellent Customer interaction, Communication and Teamwork skills Ability to do multi-tasking in Technical and Managerial Roles Should have experience in handling >5M instance count , 1.5GHz frequency designs. Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.Thanks and Regards.

Job DescriptionResponsibilities:Preparation of digital design test plan from requirements using Cadence-vManager / vPlannerDefinition and creation of UVM-SV test environment, test plans, tests, and functional coverageVerification of signal processing and control algorithms using Cadence and MathWorks toolsAnalysis of test results, improving test coverage, and debug of unexpected design behaviorRunning and maintenance of regression runs0p-Preparation and/or leading of verification reviewsModification and/or debug of Simulink models in mixed signal test environmentCoordination of verification activities with abroad team membersCooperation with system engineering team on Jama requirementsMandatory skills:Possess at least a BSEE (MSEE preferred)Should have 6-8yrsl years' experience in digital design and/or digital verificationMust be knowledgeable in digital design fundamentalsKnowledge of Universal Verification Methodology, SystemVerilog assertions, and Cadence verification tools is a mustExperience with the usage of Jama requirements management, MATLAB/Simulink model, and Python programming is a strong plusSkills, Knowledge, and AptitudesExcellent communication, documentation, problem-solving and analytical skills are requiredAble to solve challenging problems during verification and debugAbility to supervise and mentor junior engineers