Bitsilica Private Limited
Hyderabad, Telangana

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RTL Design Engineer

Bitsilica Private Limited

Verilog Digital Design
Open Positions: RTL DESIGN EngineerEducation: M.Tech (2022, 2021,2020,2019,2018 .........)B.Tech (2020, 2019,2018,2017...........)Skills Required: Strong in Digital Electronics & Verilog.Knowledge in LINT, CDC, Spyglass would be an added advantage.Experience: 0-4 YearsLocation: Hyderabad / BangaloreAvailability: Immediate
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