Hands-on in Verilog/ VHDL Hands-on in Perl/ Unix scripting Hands on in SoC level RTL integration Hands on in Clock Domain Crossing (CDC) checks, Linting, equivalence checks Experience in Digital module micro-architecture and design Experience in basic RTL simulation IP generation enhancement kind of work Good knowledge of Synthesis, STA and DFT aware design. Good knowledge of ARM subsystem, I2C protocol, AMBA bus Understanding of Power Domains and low power design techniques Familiar with DSP subsystems and high speed interfaces(e.g. SERDES, GigE, 10GE) Ability to lead & motivate a team of Engineers