Strong back ground of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis,Static Timing and Signal Integrity. Hands-on experience on technology nodes like14nm, 10nm Good knowledge of EDA tools from Synopsys, Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS androuting. Hands on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC,VOLTAS) Perform Unit testing of independent features, develop test cases and help of release testing