Physical back end including Formal Verification, Timing Closure, ECOs, Static Timing Analysis, Power Analysis, Power Analysis tools, Library files. Experience with common serial protocols such as I2C, SPI etc., Expert at simulation analysis of analog behavior including a deep understanding of basic (R/L/C/Tr) element fabrication process, simulation models and model accuracy. Digital /Arch design, verification based on SV/UVM. SPICE simulator types with deep knowledge of tradeoffs such as power modeling, SPICE and fast SPICE, noise, transient, and Monte Cario Simulations Full physical verification flow and tools