5

Cadence Virtuoso Jobs

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  • 2 - 5 yrs
  • Bangalore
EDA Perl Developer Python Cadence Virtuoso Synopsys Standard Cell Design Cell Design CMO Transistor Debugging PPA SRAM
* * Were Hiring: Memory Design Engineer Bangalore** Looking for talented *Memory Design Engineers to join our semiconductor design team* in Bangalore!* *What Youll Do:** Design & validate *SRAM/memory compilers and high-performance cache instances** Optimize Power, Performance & Area (PPA)* Work on circuit simulations, debugging, and layout integration using EDA tools (Cadence/Synopsys)* *What Were Looking For:** 2+ years in SRAM/memory design & characterization* Strong knowledge of CMOS, high-speed/low-power design, and PPA trade-offs* B.E./M.E. in Electronics, Electrical, or VLSI* Scripting (Perl/TCL/Python) a plusIf youre passionate about memory design innovation, lets connect! Drop your resume at 9042185651 or *mail your resume* at Pratishtha.B@orglinked.co.in
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Analog Layout Engineer

Eteam Infoservices

  • 4 - 8 yrs
  • 25.0 Lac/Yr
  • Hyderabad
Analog Layout Analog Design Engineer Layout Designer Layout Design Analog Layout Design Designing Layout Designing Cadence Virtuoso Virtuoso Virtuoso Layout Editor
Develops and prepares multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots.May check design layouts and detailed drawings.4-7 years of experience.Mandatory Skills:Virtuoso Layout EditorLayout designSemiconductor Device Fundamentals
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Research Analyst Jobs (Marthandam)

Kenfra Research Solutions

  • 1 - 7 yrs
  • 4.0 Lac/Yr
  • Marthandam Kanyakumari
Cadence Virtuoso Simulink MATLAB NS3 Content Writer Technical Writer Research Assistant Network Simulator
Looking for Research Assistants / Programmers with a minimum experience of 1 year.Must have Experience in Writing Research papers and Thesis.OrProgrammers should be proficient in Simulink, Ns3, Cadence, Python, MATLAB, and Siemens.Job Location: Marthandam
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Software Programmer

Panacorp Software Solutions

  • 1 - 5 yrs
  • 2.5 Lac/Yr
  • Nagercoil Kanyakumari
Java Programmer Python Matlab Programmer Ansys Cadence Virtuoso Walk in
Developing the coding, designing as well as simulation oriented programming for Research methodology . Expertise in MATLAB,SIMULINK, PYTHON, NS2 ,NS3 , ANSYS/ HFSS , CADENCE, JAVA,J2EE .
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Analog Layout Engineer

Cientra Tech Solution

  • 2 - 5 yrs
  • 20.0 Lac/Yr
  • Bangalore
VLSI-Very Large Scale Integration Analog Design Cadence Virtuoso Analog Layout
Job Description- Candidate should have good exposure of analog layout concepts like matching, shielding etc.- The selected candidate will work on floorplan, Layout and verification(DRC/LVS) of various analog and mixed signal blocks like amplifiers, references, regulators (LDO/DCDC Buck, Boost, Multiphase), PLL, ADC, DAC across a wide range of technologies from scratch.- Will have to interact with design teams to ensure on time meeting all the design requirement.- Must be technically independent, and able to work in a multi-site team environment.- Strong verbal & written communication skills are desired
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