Analog Design Design EngineerCell Layout DevelopmentMemory DevelopmentWork From HomeWalk in
1. Analog Memory leaf cell layout development/ 5 yrs+/ Bangalore Memory leaf cell layout development Understanding of Memory Compiler development flow Block and top level integration. Quality and timely delivery EM-IR, area intensive layouts, Quality checks (QC) Exposure to lower nodes like 7nm, 5nm and below Good debugging skill Understanding of DFM