Posted on 39 days ago
Mindmates Technologies Pvt. Ltd.
RS 6,00,000 To 18,00,000 Noida
Looking for a Senior Engineer with 3-7 years of experience in digital design verification domain. Technical Know-How Needed - Good hands-on experience of System Verilog & uVM (Universal Verification Methodology) - Capable of developing ...
Key Skills : System Verilog,UVM,Verilog HDL,Functional Coverage,Assertions
RS 2,00,000 To 3,00,000 Mumbai
VLSI Design Engineers has a training program for 6 - 9 months and work in Design, Modeling, Verification, FPGA Validation, and Product Validation for IPs, FPGAs, ASICs and SOCs as well as EDA Products working in areas of Verilog, SystemVerilog and V...
Key Skills : Logic Design,HDL,RTL,VHDL,Verilog,System Verilog,Verification Engineer