ASIC Design Verification Engineer

Klaxon India

4 - 8 Years
15 Openings
10.0-30.0 Lac/Yr
Ahmedabad

Key Skills

HVL SVA SV Design Verification Engineer Design Engineer

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Job Description

Minimum 2 years of experience in System Verilog HVL SVA Assertions. Must have executed at-least 2 SoC/IP Formal Verification signoff projects. Must have used Synopsys VC Formal , Cadence Jasper or Questa Formal Tools comprehensively

Hands on experience of developing Formal SV assertion/checkers, coverage register, regressions.

� Functional Checks/Assertions based Property coding to verify RTL Structures

� Data Path, Security, Register, Functional Safety and X Prorogation Verification

� Connectivity Checks on IP/SoC connections

� Fault Analysis using Formal Test bench Analyzer

� Formal Coverage and Regressions

Experience : 4 - 8 Years

No. of Openings : 15

Education : B.Tech/B.E

Role : Design Verification Engineer

Industry Type : Engineering / Cement / Metals

Gender : [ Male / Female ]

Job Country : India

About Klaxon India

Klaxon India is a reliable Placement Company based in Bangalore (Karnataka). In order to cater various requirements of the candidates, we are indulged in offering impeccable services to our clients. In addition to this, we are also engaged in offering first class services like HR Consultancy, Training Services, Career Consultant, Domestic Placement, Overseas Placement, Recruitment Consultant and Event Security Management. We have a team of experts who are actively involved in providing the best to our clients. Moreover, we take care of business interests and refer candidates that take the future of the company ahead.