Expertise in RTL, Logic design
Experience inRTL Design
Good hands on experience in Logic design
Experience of Micro Architecture preparation
Coding Experience in Verilog, System Verilog HDL languages
Experienced in Developing Environments for Li...
VLSI Design Engineers has a training program for 6 - 9 months and work in Design, Modeling, Verification, FPGA Validation, and Product Validation for IPs, FPGAs, ASICs and SOCs as well as EDA Products working in areas of Verilog, SystemVerilog and V...
1.Expertise in ASIC/SoC verification using HVLs. Knowledge of networking protocols will be an added advantage.
2.Expertise in SystemVerilog, Verification Methodologies such as OVM,UVM,etc.
3.Should have worked on at least one full-chip or module-le...