Adept Chips Hyderabad, Telangana

Work Location Hyderabad Experience 2 - 10 years Verification Engineer with 2-10 years of relevant experience in HVLs like SystemVerilog/SystemC and methodologies like UVM/OVM/VMM. Candidate should have excellent communication skills. Hands on experience in PCI Express or USB3.0 or MIPI is a plus. Familiar with interface protocols like AMBA AXI, AHB and APB. Candidate will be responsible for testbench development and verification activities individually with/without guidance. Candidate should have involved in developing testcases, test plans and reviews of documents and code. Candidate will be responsible for successful delivery to clients for given tasks/module of Formal Verification. Familiar with Perl, Shell Scripting.