Required Skills :
- Physical Design which include Floor Planning, Timing Closure, Place and route.
- Knowledge of full-chip integration issues
-Knowledge of Parasitic Interconnect modeling and issues
- Cell and Transistor level parasitic ...
Job Responsibility Involves Full Ownership of Complete Memory Development Process Starting from Freezing of Specifications , Forming the Verification Plan , Ensuring the Timely Approvals from Customer , Self Execution of Memory Design , Verification.
Providing accurate schedules
Meeting project milestone deadlines
Full self-sufficiency in debugging complex verification failures
Mentoring of junior layout designers.
Delivering high quality layout that conforms to all design requirements.