RS 1,00,000 To 3,00,000 p.a. Hyderabad, Secunderabad
- Engineer Will Be Responsible for Designing the Asic to Meet the Specifications Defined. - Responsible for Defining and Implementing Micro-architecture Design and Development of Various Functional Blocks. - Responsible for Design of Soc-level Log...
Key Skills : soc design,asic design,rtl design,dft system verilog,digital designer,digital artist